Single Die Multi-Layer Interconnect Bonding
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Solution Overview
Problem
The challenge in semiconductor manufacturing is the contamination of particles and defects in multi-layer interconnect structures, which increases as the dimensions of devices and metallic layers shrink, leading to reduced yields and longer processing times in traditional methods.
Innovation Solution
The method involves forming a single die by bonding metallic layers from two substrates, one with front-end-of-line (FEOL) and the other with back-end-of-line (BEOL) processing, allowing for parallel processing and reducing cycle time, and enabling the use of reclaimed substrates to lower costs and improve yield.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If traditional single die multi-layer interconnect structures are used, then device integration is achieved, but particle contamination and defects increase as dimensions shrink, reducing yield
Solution Approach 1:
The patent divides the single die fabrication into two separate substrates: a first substrate containing the active device and a second substrate containing only metallic interconnect layers. This segmentation allows each substrate to be processed independently, reducing the cumulative defect risk associated with forming all metallic layers on a single substrate with shrinking dimensions.
2Speed
If the number of metallic layers is increased to achieve high-speed performance, then transistor operational speed improves, but particle contamination becomes more serious and yield decreases
Solution Approach 1:
The patent segments the multi-layer interconnect structure formation by placing some metallic layers on the first substrate with the active device and other metallic layers on the second substrate without active devices. This allows parallel processing of multiple metallic layers across separate substrates, reducing the cumulative contamination risk while achieving the required number of interconnect layers for high-speed operation.
3Device complexity
If all metallic layers are formed on a single substrate, then a complete interconnect structure is achieved, but processing time increases due to sequential operations
Solution Approach 1:
The patent segments the interconnect structure formation across two separate substrates, allowing parallel processing of different metallic layers and associated dielectric layers on each substrate. This parallelism significantly reduces the overall processing cycle time compared to forming all layers sequentially on a single substrate, while still achieving the complete multi-layer interconnect structure through subsequent bonding.
Solution Approach 2:
The patent performs preliminary actions by forming metallic layers and dielectric structures on the second substrate independently before bonding to the first substrate. This preliminary formation of interconnect layers on a separate substrate allows these layers to be prepared in advance, enabling parallel processing and reducing the total manufacturing cycle time.
4Area of moving object
If dimensions of devices and metallic layers are reduced for high-integration, then integration density improves, but particle contamination impact increases
Solution Approach 1:
The patent segments the fabrication process into two separate substrates, which reduces the cumulative probability of particle contamination affecting the entire interconnect structure. By dividing the process, a particle defect on one substrate does not compromise the entire device, thereby mitigating the impact of contamination as dimensions are reduced for higher integration density.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach reduces the overall cycle time by approximately 40% and maintains higher yields by separating the processing of active and non-active device layers, thereby minimizing the impact of defects and reducing the number of wafers needed for production.
Implementation Method 1
The at least one first metallic layer is bonded with the at least one second metallic layer such that the first substrate and the second substrate constitute a single die
Data Source
AI summary
A method for forming a single die includes forming at least one first active device over a first substrate and at least one first metallic layer coupled to the first active device. At least one second metallic layer is formed over a second substrate, wherein the second substrate does not include any active device. The at least one first metallic layer is bonded with the at least one second metallic layer such that the first substrate and the second substrate constitute a single die.