Single-Die Semiconductor Integration Using Selective Epitaxy
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Solution Overview
Problem
The integration of silicon-based and heterostructure-based electronic components in separate dice leads to increased manufacturing costs, energy consumption, and poor electrical performance due to parasitic capacitances and complex electrical connections.
Innovation Solution
A manufacturing process that integrates both silicon-based and heterostructure-based electronic components in a single die, utilizing a substrate with epitaxial layers and a growth mask to ensure high crystallographic quality and direct electrical connections, thereby reducing the need for separate dice and associated parasitic capacitances.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If silicon-based and heterostructure-based electronic components are integrated in separate dice, then each component type maintains its optimal crystallographic quality and electrical performance, but the overall device occupies larger area, has higher manufacturing cost, and introduces parasitic capacitances that degrade electrical performance
Solution Approach 1:
The patent merges silicon-based and heterostructure-based electronic components into a single integrated die by growing both component types on a common semiconductor substrate. The substrate contains a first region with silicon-based components and a second region with heterostructure-based components, eliminating the need for separate dice and reducing overall device area while maintaining crystallographic quality through controlled epitaxial growth processes.
2Manufacturing precision
If separate dice are used for silicon-based and heterostructure-based components, then each die can be optimized independently, but manufacturing cost and energy consumption increase
Solution Approach 1:
The patent segments the substrate into distinct first and second regions, where the first region is dedicated to silicon-based electronic components and the second region is dedicated to heterostructure-based electronic components. This spatial segmentation allows independent optimization of each component type while sharing a common substrate, reducing manufacturing complexity and cost compared to producing separate dice.
3Adaptability or versatility
If separate dice are bonded together to integrate different components, then component optimization is maintained, but parasitic capacitances are introduced that reduce electrical performance
Solution Approach 1:
The patent combines silicon-based and heterostructure-based electronic components into a single integrated die structure, eliminating the need for die bonding. This direct integration on a common substrate removes the parasitic capacitances that would be introduced by bonding interfaces and inter-die connections, thereby improving electrical performance while maintaining the ability to optimize each component type independently through regional segmentation.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach allows for a compact semiconductor electronic device with improved electrical performance, reduced manufacturing costs, and lower energy consumption by eliminating the need for separate dice and simplifying electrical connections.
Implementation Method 1
operation of such electronic components is based upon the electronic properties of a heterojunction between two different semiconductor materials. In detail, in HEMTs, the conductive channel is based upon formation of layers of two-dimensional electron gas (2DEG) with high-mobility electrons that form at a heterojunction, i.e., at the interface between semiconductor materials that have different band gaps.
Implementation Method 2
The heterostructure-based electronic components are integrated in a heterostructure grown epitaxially on a silicon wafer, or else on a substrate of sapphire (Al2O3) or silicon-carbide (SiC).
Data Source
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Figure 3A
AI summary
To manufacture a semiconductor electronic device (1) a wafer (100) is provided that has a substrate layer (18) of semiconductor material having a first portion (101A) and a second portion (101B) distinct from the first portion. An epitaxial region (23, 106) of a single semiconductor material is grown on the first portion (101A) of the substrate layer. An epitaxial multilayer (49, 114) having a heterostructure (50) is grown on the second portion (101B) of the substrate layer. A first electronic component (5A, 5B, 5C, 5D) based upon the single semiconductor material is formed starting from the epitaxial region (23, 106) and a second electronic component (7) based upon a heterostructure is formed starting from the heterostructure. To grow an epitaxial multilayer, a growth mask (103) is formed on the substrate layer (18); an opening is made in the growth mask (103), thereby exposing the second portion of the substrate layer; and the epitaxial multilayer is grown on the second portion of the substrate layer.