Single-Die Semiconductor Integration of Silicon and Heterostructures
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Solution Overview
Problem
The integration of silicon-based and heterostructure-based electronic components in a single semiconductor electronic device poses challenges due to the high area occupation, manufacturing cost, power consumption, and electrical performance issues caused by parasitic capacitances, resistances, or inductances introduced by electrical connections between dice.
Innovation Solution
A manufacturing process that integrates silicon-based and heterostructure-based electronic components in a single die, utilizing a substrate with epitaxial layers and a growth mask to grow the epitaxial multilayer, allowing for direct electrical connection between components and reducing parasitic effects.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If silicon-based and heterostructure-based electronic components are integrated in different dice, then the manufacturing process of each component type can proceed independently without mutual interference, but the area occupation and manufacturing cost increase significantly
Solution Approach 1:
The patent merges silicon-based and heterostructure-based components into a single integrated die, eliminating the need for separate dice and inter-dice connections. This combining approach reduces area occupation while maintaining independent manufacturing capabilities through selective growth regions and masking techniques that allow sequential formation of different component types within the same substrate.
2Ease of manufacture
If silicon-based and heterostructure-based electronic components are integrated in different dice and bonded together, then manufacturing independence is maintained, but parasitic capacitances, resistances, and inductances are introduced that degrade electrical performance
Solution Approach 1:
The patent combines both component types within a single die to eliminate inter-dice bonding interfaces, thereby removing parasitic capacitances, resistances, and inductances associated with separate dice connections. This integration approach directly improves electrical performance while maintaining manufacturing independence through controlled epitaxial growth and masking processes.
3Reliability
If heterostructure-based components are grown using high thermal budget, then the quality and performance of HEMT devices are improved, but silicon-based components may be damaged or degraded
Solution Approach 1:
The patent segments the substrate into distinct growth regions: a first growth region for silicon-based components and a second growth region for heterostructure-based components. By using a growth mask to define these regions, the process allows high thermal budget epitaxial growth in the second region while protecting silicon-based components in the first region from thermal damage, thus achieving both high HEMT performance and silicon component integrity.
4Area of stationary object
If silicon-based and heterostructure-based components are integrated in a single die, then area occupation is reduced and electrical performance is improved, but the manufacturing process complexity increases
Solution Approach 1:
The patent uses a growth mask to segment the substrate into distinct growth regions, enabling selective epitaxial growth of silicon-based and heterostructure-based components in separate areas. This segmentation approach simplifies the manufacturing process by allowing sequential formation of different component types without mutual interference, reducing overall process complexity despite integration benefits.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enables the combination of silicon-based and heterostructure-based components in a single die with improved electrical performance, reduced manufacturing costs, and lower power consumption, while maintaining small dimensions.
Implementation Method 1
growing thereon an epitaxial multilayer comprising a heterostructure wherein at least part of the heterostructure is grown directly on the substrate
Data Source
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Figure 3A
AI summary
For manufacturing a semiconductor electronic device (1) a wafer (100) is provided which has a substrate layer (18) of semiconductor material having a first portion (101A) and a second portion (101B) distinct from the first portion. An epitaxial region (23, 106) of a single semiconductor material is grown on the first portion (101A) of the substrate layer. An epitaxial multilayer (49, 114) having a heterostructure (50) is grown on the second portion (101B) of the substrate layer. A first electronic component (5A, 5B, 5C, 5D) based on the single semiconductor material is formed from the epitaxial region (23, 106) and a second electronic component (7) based on heterostructure is formed from the heterostructure. Forming a first electronic component comprises forming a plurality of doped regions (25A, 25B, 27, 29A, 29B, 31) in the epitaxial region (23), after the step of growing an epitaxial multilayer.