Single Diffusion Break Isolation for Gate-All-Around FET Devices
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Solution Overview
Problem
As semiconductor devices scale to smaller dimensions, traditional isolation methods like shallow trench isolation and diffusion breaks become inefficient in terms of footprint area usage, especially at the 7-nm technology node and beyond, leading to reduced packing densities and increased complexity in forming effective isolation structures for gate-all-around FET devices.
Innovation Solution
The implementation of single diffusion break isolation structures, which involve a dummy gate structure between source/drain layers of gate-all-around FET devices, allows for efficient electrical isolation while minimizing footprint area consumption by using a single isolation structure instead of double diffusion breaks.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If double diffusion break isolation structures are used, then electrical isolation between FET devices is achieved, but footprint area is significantly consumed leading to reduced packing densities
Solution Approach 1:
The isolation structure is segmented into multiple functional regions: a first isolation region with first isolation material, a second isolation region with second isolation material, and a third isolation region with third isolation material. This segmentation allows each region to contribute differently to the isolation function, achieving effective electrical isolation while minimizing the total footprint area compared to traditional double diffusion break structures.
2Reliability
If shallow trench isolation methods are used, then active device areas are isolated, but a significant amount of footprint area is consumed
Solution Approach 1:
Different isolation materials are used in different local regions of the isolation structure. The first isolation material is used in the first isolation region, the second isolation material in the second isolation region, and the third isolation material in the third isolation region. This local quality approach allows optimization of isolation properties in each region while minimizing overall footprint area.
3Productivity
If device scaling continues to smaller dimensions, then integration density increases, but forming effective isolation structures becomes increasingly difficult
Solution Approach 1:
The isolation structure is formed with preliminary patterning steps that define the first, second, and third isolation regions before final isolation material deposition. This preliminary action approach simplifies the overall fabrication process by breaking down the complex isolation structure formation into manageable sequential steps, making it feasible to implement at smaller technology nodes.
Data Source
AI summary
Devices and methods are provided for forming single diffusion break isolation structures for integrated circuit devices including gate-all-around FET devices such as nanosheet FET devices and nanowire FET devices. For example, a semiconductor integrated circuit device includes first and second gate-all-around field-effect transistor devices disposed in first and second device regions, respectively, of a semiconductor substrate. A single diffusion break isolation structure is disposed between the first and second device regions. The single diffusion break isolation structure includes a dummy gate structure disposed on the semiconductor substrate between a first source/drain layer of the first gate-all-around field-effect transistor device and a second source/drain layer of the second gate all-around field-effect transistor device. The single diffusion break isolation structure is configured to electrically isolate the first and second source/drain layers.