Single-Edge DAC Driver Circuit for Low Timing Skew
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Solution Overview
Problem
Current DAC designs face challenges in achieving low timing uncertainty and timing skew, particularly in high-speed applications like 5G wireless communication, where stringent requirements for linearity, SNR, and low power consumption are necessary, leading to complex circuitry and exponential growth in power and area with performance targets.
Innovation Solution
A low timing uncertainty switch driver circuit is introduced, utilizing single-ended and differential driver circuits with positive and negative single-edge latches, where clock signals are synchronized to control the overlap time of switch control signals, reducing the complexity and length of timing critical paths by generating on-state overlap globally and optimizing delay periods for each DAC cell.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If long signal paths are used for timing critical events in prior art DAC designs, then on-state overlap can be generated, but timing skew increases and power consumption grows exponentially with performance targets
Solution Approach 1:
The patent segments the timing control function by separating the generation of on-state overlap signals from the data signal path. The clock signal is divided into multiple phases (e.g., phi1, phi2, phi3, phi4) that are distributed to different latch circuits, allowing independent control of switch timing without extending the critical data path
Solution Approach 2:
The patent introduces clock phase signals as intermediary elements that mediate between the global clock and the switch control. These phased clock signals act as intermediaries to coordinate the timing of multiple switches without requiring long direct signal paths between them
2Reliability
If multiple signal paths are used to propagate four events for on-state overlap, then timing control is achieved, but power consumption and area grow exponentially
Solution Approach 1:
The patent makes the phased clock signals universal by using the same set of phases (phi1, phi2, phi3, phi4) to control multiple switches and multiple DAC cells simultaneously. This multi-functional clock distribution eliminates the need for separate signal paths for each switch or cell, reducing power consumption and area
Solution Approach 2:
The patent merges the timing control function into a unified clock distribution network that serves all switches and cells. Instead of having separate control paths for each event, the phased clocks are combined into a single distribution system that coordinates all timing-critical operations
3Manufacturing precision
If circuit parameters vary randomly for each die, then manufacturing variability increases, but delay variation can be minimized by optimizing device count and intermediate nodes
Solution Approach 1:
The patent performs preliminary action by pre-synchronizing data signals to the clock phases before they reach the DAC cells. The latching operation is performed in advance at specific clock edges, ensuring that all data is captured and stabilized before the critical switching event, thereby minimizing delay variation without requiring complex compensation circuits
Data Source
AI summary
A single ended driver circuit (100) for a digital to analog conversion, DAC, cell is presented. The driver circuit (100) comprises one positive single-edge latch (200) configured to provide a positive edge latched data signal (S+) by latching a positive edge of a data signal (D) synchronized by a first clock signal (CLK1), and a negative single-edge latch (300) configured to provide a negative edge latched data signal (S−) by latching a negative edge of the data signal (D) synchronized by a second clock signal (CLK2). The positive edge latched data signal (S+) and the negative edge latched data signal (S−) are combined to provide a drive signal (S) having a positive edge synchronized by the first clock signal (CLK1) and a negative edge synchronized by the second clock signal (CLK2). The positive single-edge latch (200) and the negative single-edge latch (300) are also presented.