Shared-Clock Single-Edge Flip-Flops With Fewer Internal Clock Devices
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Solution Overview
Problem
Current flip-flop designs in digital synchronous systems are limited in reducing clocking power, as they cannot further downsize devices due to process technology scaling, leading to increased power consumption and heat dissipation, especially in high-frequency CPUs and AI accelerators.
Innovation Solution
The development of single-edge triggered flip-flops with reduced shared clock pin capacitance and time-borrowing internally stitched Octa flip-flops, which reduce the number of internal clock devices from 8 to 6, enabling significant power savings by intelligent clock sharing and internal stitching techniques.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of stationary object
If conventional multi-bit flip-flop approaches are used, then area efficiency is improved, but clocking power consumption increases due to more internal clock devices
Solution Approach 1:
The patent merges multiple flip-flops into a single multi-bit flip-flop structure where multiple data inputs (D0-D3) and outputs (Q0-Q3) are combined into one integrated circuit unit. This merging allows shared clocking infrastructure and reduced overall area while maintaining functionality of multiple independent flip-flops
Solution Approach 2:
The clocking function is segmented into separate clock inputs (CLK0, CLK1, CLK2, CLK3) for different groups of flip-flops within the multi-bit structure. This segmentation allows independent clock control for different segments, enabling power optimization by clocking only active segments and reducing unnecessary switching activity in idle portions
2Use of energy by moving object
If device size is reduced to lower power consumption, then power efficiency improves, but process technology scaling limits are reached preventing further downsizing
Solution Approach 1:
Multiple flip-flops are merged into a single multi-bit flip-flop standard cell, reducing the total number of separate devices required. This consolidation achieves area efficiency and power reduction without requiring further downsizing of individual transistor devices, which are already at minimum viable sizes due to process technology constraints
Solution Approach 2:
The multi-bit flip-flop structure provides universal functionality by integrating multiple independent flip-flop units into one standardized cell that can replace multiple separate flip-flops. This multi-functional design achieves area and power savings through consolidation rather than device miniaturization
3Productivity
If deeper pipelines are implemented to increase frequency, then processing performance improves, but clocking power consumption increases
Solution Approach 1:
The clocking system is segmented into multiple independently controllable clock inputs (CLK0-CLK3) that can be selectively enabled or disabled based on pipeline stage activity. This segmentation allows the system to support deep pipelines for high-frequency operation while reducing clocking power by deactivating clocks to idle pipeline stages, achieving performance without proportional power increase
Data Source
AI summary
A new family of shared clock single-edge triggered flip-flops that reduces a number of internal clock devices from 8 to 6 devices to reduce clock power. The static pass-gate master-slave flip-flop has no performance penalty compared to the flip-flops with 8 clock devices thus enabling significant power reduction. The flip-flop intelligently maintains the same polarity between the master and slave stages which enables the sharing of the master tristate and slave state feedback clock devices without risk of charge sharing across all combinations of clock and data toggling. Because of this, the state of the flip-flop remains undisturbed, and is robust across charge sharing noise. A multi-bit time borrowing internal stitched flip-flop is also described, which enables internal stitching of scan in a high performance time-borrowing flip-flop without incurring increase in layout area.