Single-Electron Transistor with Wrap-Around Gate for High-Temperature Operation
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Solution Overview
Problem
Conventional CMOS processes face limitations in scaling down logic devices, and single-electron transistors (SETs) operating by quantum tunneling effects are needed to achieve smaller scales, but they require high-temperature operation and precise capacitance control.
Innovation Solution
A method for forming a single-electron transistor with a quantum dot surrounded by a gate stack, using sacrificial layers and etching techniques to create a fin structure with a wrap-around gate, allowing for high-temperature operation and low self-capacitance, enabling efficient quantum tunneling.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Length of moving object
If conventional CMOS processes are used to scale down logic devices, then manufacturing capability is maintained, but device scaling limit is reached
Solution Approach 1:
The patent introduces sacrificial layers (oxides or nitrides) as intermediary structures that enable the formation of wrap-around gates. These sacrificial layers are deposited conformally on fin structures, then selectively removed to create cavities that allow gate material to wrap around the active channel region, achieving 3D gate control necessary for continued scaling beyond conventional CMOS limits
Solution Approach 2:
The invention transitions from planar 2D gate structures to 3D wrap-around gate structures by utilizing vertical fin structures and conformal deposition techniques. The gate material wraps around the active layer in three dimensions, providing enhanced gate control and enabling continued scaling at smaller dimensions where conventional planar transistors reach their physical limits
2Length of moving object
If single-electron transistors are implemented for smaller scales, then device size is reduced, but temperature operation requirement increases
Solution Approach 1:
The patent embeds quantum dots (nanoscale active regions) within the wrap-around gate structure, creating a nested configuration where the quantum dot is surrounded by gate material on multiple sides. This nested structure provides strong electrostatic control over the quantum dot, enabling stable single-electron tunneling operation at elevated temperatures by effectively confining carriers and reducing thermal effects
3Productivity
If single-electron transistors are implemented for smaller scales, then logic device performance is improved, but capacitance control precision requirement increases
Solution Approach 1:
The patent creates locally optimized electric field distributions by positioning gate material strategically around specific regions of the quantum dot. The wrap-around gate structure provides non-uniform electric field confinement that is highly localized to the quantum dot region, enabling precise control over tunneling barriers and capacitance values. This local quality control allows independent tuning of source and drain tunneling characteristics
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The method enables single-electron transistors to operate effectively at high temperatures with precise control over capacitance, facilitating smaller device scales and improved logic device performance.
Implementation Method 1
Single-electron transistors (SETs), which operate by quantum tunneling effects
Data Source
AI summary
Transistors and methods of forming the same include forming a fin that has an active layer between two sacrificial layers. Material is etched away from the two sacrificial layers in a region of the fin. A gate stack is formed around the active layer in the region. The active layer is etched after forming the gate stack to form a quantum dot.