Single-End Read Module Noise Immunity via Global Bit Line Driver
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Solution Overview
Problem
Conventional single end read modules for register files are susceptible to noise-induced failures, particularly in low voltage supply designs, due to the vulnerability of the latch mechanism, leading to reliability issues.
Innovation Solution
The proposed single end read module incorporates a global bit line driver with a PMOS transistor pre-charge module and a CMOS device in the global bit line driver, eliminating the need for a latch and enhancing noise resistance by selectively pre-charging and responding to the value stored in memory cells.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a latch mechanism is used in the conventional single end read module, then the read operation can be enabled, but the module becomes susceptible to noise-induced failures leading to reliability issues
Solution Approach 1:
The patent removes the vulnerable latch mechanism from the read module architecture. Instead of using a latch to hold the read data, the invention directly couples the local bit line to the global bit line through a selection mechanism, eliminating the noise-sensitive latch component that caused reliability issues in conventional designs
Solution Approach 2:
The patent introduces a selection mechanism (selection signal-controlled switch) as an intermediary between the local bit line and global bit line. This mediator allows controlled connection without requiring a latch, thereby achieving read operation enablement while avoiding noise susceptibility
2Use of energy by moving object
If the latch mechanism is used in low voltage supply design, then power consumption is reduced, but noise-induced failures increase causing serious reliability issues
Solution Approach 1:
The patent eliminates the latch mechanism entirely from the low voltage read module design. By removing the latch, the design avoids the noise-induced failure problems that plague low voltage latch-based designs, while maintaining power efficiency through direct bit line coupling controlled by selection signals
3Device complexity
If a conventional single end read module with latch is used, then the structure is simple, but noise on the global bit line causes latch flipping and read operation failure
Solution Approach 1:
The patent removes the latch component from the read module, simplifying the structure by eliminating unnecessary components while simultaneously improving reliability. The direct coupling approach requires fewer components than a latch-based design, achieving both structural simplicity and noise immunity
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This design improves the reliability of read operations by reducing noise-induced failures, making it suitable for low voltage supply and high noise environments without increasing layout area, thus providing a more reliable solution for register file access.
Implementation Method 1
a output terminal coupled to a global bit line for selectively pre-charging the global bit line at a default voltage in response to a local pre-charge signal
Implementation Method 2
a first NMOS transistor having a source coupled to ground, a drain coupled to a global bit line, and a gate coupled to the local I/O module; a first PMOS transistor having a drain coupled to the drain of the first NMOS transistor, and a gate controlled by a select signal
Data Source
AI summary
A read module for register files includes at least one local I/O module coupled to a memory cell for outputting a value stored in the memory cell; and at least one global bit line driver having an input terminal coupled to the local I/O module, and a output terminal coupled to a global bit line for selectively pre-charging the global bit line at a default voltage in response to a local pre-charge signal, and outputting the value stored in the memory cell to the global bit line when the local pre-charge signal is not asserted.