Single-Ended Column ADC Comparators for Low-Noise Image Sensors
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Solution Overview
Problem
Conventional ramp analog-to-digital converters (ADCs) used in image sensors suffer from high noise levels and elevated power consumption due to the use of differential comparators.
Innovation Solution
The implementation of low noise single-ended comparison stages in the analog-to-digital converter circuitry, which reduces power consumption and minimizes noise levels by using single-ended voltage comparison circuits instead of differential comparators.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If differential comparators are used in ramp ADCs, then high bit resolution can be achieved, but noise levels and power consumption increase
Solution Approach 1:
The patent changes the fundamental operating parameters of the comparator by transitioning from differential to single-ended architecture. This parameter change modifies the noise characteristics and power consumption while maintaining the ability to achieve high bit resolution through the ramp ADC conversion process
2Measurement precision
If differential comparators are used in ramp ADCs, then high bit resolution can be achieved, but power consumption increases
Solution Approach 1:
The patent changes the fundamental operating parameters of the comparator by transitioning from differential to single-ended architecture. This parameter change modifies the power consumption characteristics while maintaining the ability to achieve high bit resolution through the ramp ADC conversion process
3Object-generated harmful factors
If single-ended comparison stages are used, then noise levels and power consumption are reduced, but device complexity changes
Solution Approach 1:
The patent extracts the differential structure from the comparator design, retaining only the essential single-ended comparison functionality. This extraction simplifies the circuit architecture by removing redundant differential pairs while maintaining the core comparison operation needed for ADC conversion
Data Source
AI summary
An image sensor may include an array of imaging pixels arranged in rows and columns. Each column of pixels can be coupled to a column analog-to-digital converter (ADC) via a pixel output line. The column ADC can include a first low noise single-ended comparison stage, a second low noise single-ended comparison stage, a latch circuit, and a counter. The first low noise single-ended comparison stage may include one or more current source transistors, a voltage ramp generator, a common source amplifier transistor, one or more autozero components, one or more capacitors such as a noise filtering capacitor, and a voltage clamping circuit. The voltage ramp generator can output an increasing voltage ramp or a decreasing voltage ramp.