Single-Ended Sense Amplifier With Hierarchical Bit Lines
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Solution Overview
Problem
Conventional differential current sense amplifiers in semiconductor devices occupy a large surface area, leading to increased chip area and current consumption, especially when used in memory cells with high resistance values.
Innovation Solution
A semiconductor device utilizing a single-ended sense amplifier with a hierarchical bit line structure, where a single MOS transistor amplifies signal voltage, reducing bit line capacitance and enabling rapid charging and discharging, and a global bit line sense amplifier for information reading and writing control, maintaining compatibility with DRAM without increasing chip area or current consumption.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If a conventional differential current sense amplifier is used, then signal amplification is achieved, but the chip area significantly increases
Solution Approach 1:
The invention extracts the essential sensing function from the complex differential amplifier structure and implements it using a simplified single-ended amplifier configuration. By removing unnecessary differential components and using only a single sense amplifier per bit line, the chip area is significantly reduced while maintaining the core signal amplification capability needed for detecting memory cell states.
Solution Approach 2:
The invention uses a copy of the bit line signal through the hierarchical structure, where local bit line signals are amplified and then transferred to global bit lines for further processing. This allows the sensing function to be distributed and performed with simpler circuits rather than requiring full differential amplification at every stage.
2Measurement precision
If a conventional differential current sense amplifier is used, then signal amplification is achieved, but current consumption increases
Solution Approach 1:
The invention extracts only the essential amplification function needed for sensing, eliminating the power-consuming differential pair structures. By using a single-ended amplifier with controlled current sources, the current consumption is reduced while still achieving sufficient signal amplification for memory read operations.
Solution Approach 2:
The sense amplifier operates in periodic cycles, being enabled only during read operations and disabled during non-read periods. This periodic activation reduces average current consumption compared to continuously operating differential amplifiers, while still providing the necessary signal amplification when needed.
3Speed
If bit line capacitance is reduced, then charging and discharging speed increases, but signal amplification capability may be affected
Solution Approach 1:
The invention changes the operating parameters of the sense amplifier, including the transconductance of the amplifying transistor and the current source levels, to optimize the balance between speed and amplification capability. By adjusting these parameters, the amplifier can provide sufficient gain even with reduced bit line capacitance, maintaining both speed and signal detection accuracy.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution allows for efficient signal amplification by a single MOS transistor, reducing the surface area of the sense amplifier and maintaining compatibility with DRAM while keeping chip area and current consumption low.
Implementation Method 1
a first field-effect transistor that works as a single-ended sense amplifier having a gate connected to the bit line for amplifying a data signal on the bit line
Implementation Method 2
a second field-effect transistor connected to the bit line for controlling a potential of the bit line to a first predetermined potential
Implementation Method 3
a memory cell for storing information based on a resistance value between an input/output terminal and a power supply terminal, or an ON current value of a cell transistor
Data Source
AI summary
A sense amplifier in a semiconductor storage device includes a memory cell for storing information on the basis of the size of the resistance value between a signal input/output terminal and a power supply terminal, the semiconductor storage device having a structure in which the bit line capacitance during signal reading from the memory cell is reduced, wherein the amplifier amplifies a signal outputted from an input/output terminal through the use of a single MOS transistor that has a single-ended structure.