Single Ended Bitline Current Sense Amplifier for SRAM
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Solution Overview
Problem
In semiconductor memory devices, the increase in integration density leads to increased load capacitance across data lines, reducing read speed and increasing power consumption, particularly in high-performance designs above one gigahertz.
Innovation Solution
A current sense read amplifier is used, which includes a voltage regulator to maintain a constant bitline voltage, a measurement circuit to detect high and low current levels, and a generator to produce output signals based on detected currents, reducing voltage swings and power consumption.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If integration density is increased, then memory capacity is improved, but load capacitance increases and read speed decreases
Solution Approach 1:
The patent extracts the voltage regulation function from the traditional sense amplifier and implements it separately through a dedicated voltage regulator circuit. This allows the sense amplifier to focus solely on current sensing while the regulator maintains constant bitline voltage, thereby reducing capacitance effects and improving read speed without sacrificing memory capacity.
Solution Approach 2:
The patent introduces a voltage regulator as an intermediary component between the power supply and the bitline. This regulator acts as a mediator that maintains constant voltage on the bitline during sensing operations, isolating the sense amplifier from voltage fluctuations and reducing the impact of load capacitance on read speed.
2Quantity of substance
If integration density is increased, then memory capacity is improved, but power consumption increases
Solution Approach 1:
The patent separates the voltage regulation function from the sense amplifier operation. By using a dedicated voltage regulator to maintain constant bitline voltage, the sense amplifier consumes less power as it doesn't need to perform both voltage regulation and current sensing. This reduces overall power consumption while maintaining high memory capacity.
Solution Approach 2:
The patent changes the operating parameter of the bitline from variable voltage to constant voltage during sensing operations. This parameter change reduces dynamic power consumption associated with voltage swings on the bitline, thereby lowering overall power consumption while maintaining high integration density.
3Use of energy by moving object
If voltage swings on bitline are reduced, then power consumption is reduced, but signal detection capability may be affected
Solution Approach 1:
The patent replaces voltage-based signal detection with current-based signal detection. By using a sense amplifier that measures current rather than voltage swings, the system can maintain low power consumption (small voltage swings) while preserving excellent signal detection capability. The current measurement is inherently more sensitive to the small signals from memory cells.
Solution Approach 2:
The voltage regulator serves as an intermediary that enables small voltage swings on the bitline while maintaining stable operating conditions. This allows the sense amplifier to detect current changes accurately even when voltage excursions are minimized, thus reducing power consumption without compromising detection capability.
Data Source
AI summary
Single ended bitline current sense amplifier for SRAM applications. The present disclosure relates to current sense read amplifier for use as a read amplifier in a memory arrangement of memory cell groups, wherein in each of the memory cell groups cells includes at least one read port connected to a read amplifier by a bitline, and wherein said read amplifiers are connected to a data output. The current sense read amplifier includes a voltage regulator to keep a bitline voltage at a constant voltage level below a power supply voltage and above a ground, a measurement circuit to detect a high current value and a low current value in a input signal, and a generator to generate a high voltage level output signal when the high current value input is detected and to generate a low voltage level output signal when the low current level value is detected.