Single-Ended Signaling With DC-Balanced Encoding and Striping

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Solution Overview

Problem

Single-ended signaling experiences interference and noise due to shared return currents, reducing the reliability of signal transmission.

Innovation Solution

A data encoding and striping scheme is implemented for temporal DC balancing, where data segments are translated into encoded symbols and striped across multiple communication lanes using a 6-bit/7-bit encoding scheme, ensuring a balanced ratio of high and low state bits, and routed to different serializers for instantaneous DC balancing.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Ease of operation

If single-ended signaling is used for signal transmission, then the signaling method is simple and commonly used, but interference and noise occur due to shared return currents

Engineering Contradiction:
Improvesignaling method simplicityVSAvoidinterference and noise
Core Design Contradiction:
Ease of operationVSObject-affected harmful factors

Solution Approach 1:

The patent segments the data stream into multiple parallel lanes for transmission. Each lane carries a portion of the encoded data, allowing the system to maintain simple single-ended signaling while reducing interference through distribution across multiple independent paths.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The patent applies DC balancing encoding that transforms the electrical parameters of the signal by ensuring equal numbers of high and low voltage transitions. This parameter transformation maintains signal integrity and reduces noise accumulation without changing the fundamental single-ended signaling approach.

Inventive Principle:
Principle #35Parameter changes

2Device complexity

If data is transmitted without DC balancing, then the transmission process is simple, but DC voltage accumulation occurs causing signal degradation

Engineering Contradiction:
Improvetransmission process complexityVSAvoidsignal transmission reliability
Core Design Contradiction:
Device complexityVSReliability

Solution Approach 1:

The patent implements DC balancing encoding before data transmission, preliminarily adjusting the data sequence to ensure balanced DC content. This preliminary action prevents DC voltage accumulation during transmission, maintaining signal reliability without requiring complex real-time adjustments.

Inventive Principle:
Principle #10Preliminary action

Solution Approach 2:

The patent introduces an encoding layer as an intermediary between the data source and transmission medium. This intermediary transforms the original data into a DC-balanced form that is suitable for reliable single-ended transmission, separating the complexity of DC balancing from the transmission process itself.

Inventive Principle:
Principle #24Intermediary (Mediator)

3Object-affected harmful factors

If DC balancing encoding is implemented, then interference and noise are reduced, but encoding and decoding complexity increases

Engineering Contradiction:
Improveinterference and noiseVSAvoidencoding and decoding complexity
Core Design Contradiction:
Object-affected harmful factorsVSDevice complexity

Solution Approach 1:

The patent divides the encoding task into multiple independent encoders working in parallel on different data segments. This segmentation allows DC balancing to be applied to smaller, manageable portions of data, reducing the complexity burden on any single encoding unit while maintaining overall noise reduction benefits.

Inventive Principle:
Principle #1Segmentation

Data Source

PatentUS10992449B1Encoding and striping technique for DC balancing in single-ended signaling
Publication Date: 2021.04.27 CADENCE DESIGN SYST INC
  • US10992449B1 patent drawing
  • US10992449B1 patent drawing
  • US10992449B1 patent drawing

AI summary

A set of encoders within a transmitter (TX) physical layer (PHY) encode incoming data using a predefined encoder scheme by translating multiple data segments into a set of balanced bit sequences. Each data segment comprises a first number of bits and each balanced bit sequence comprises a second number of bits. A data striping component distributes the set of balanced bit sequences to a set of serializers by routing bits from particular bit positions in each balanced bit sequence to a corresponding serializer. The set of serializers generates serialized data based on the set of balanced bit sequences.