Single-Ended Receiver Circuit for High-Voltage I/O Translation
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Solution Overview
Problem
Integrated circuit designs face challenges in reliably receiving high voltage domain I/O signals due to reduced internal power supply voltages, leading to signal saturation and increased chip area requirements for separate differential and single-ended receiver circuits.
Innovation Solution
A transistor ladder voltage divider and pass gate circuit are used to divide and process high voltage domain signals, with outputs from these circuits combined by comparators to generate signals within the receiver's voltage domain, allowing for shared interface circuitry between differential and single-ended receivers.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If complex circuit designs involving source followers, voltage regulators, and level selection logic are used to interface high voltage domain I/O signals with low voltage domain receiver circuit, then the receiver can handle high voltage signals, but the device complexity increases significantly
Solution Approach 1:
The patent introduces an intermediary voltage translation mechanism using a differential receiver with controlled voltage levels. The receiver uses a first voltage level (1.8V) for internal operation and a second voltage level (3.3V) for I/O interface, with level selection logic that acts as an intermediary to translate between these domains. This intermediary approach allows high voltage signals to be received without requiring complex source followers and voltage regulators throughout the entire signal path.
Solution Approach 2:
The patent changes the voltage level parameter dynamically based on the operating mode. The level selection logic switches between different voltage levels (1.8V and 3.3V) depending on whether the receiver is operating in differential or single-ended mode. This parameter change allows the same hardware to adapt to different voltage domains without requiring separate complex circuit designs for each mode.
2Adaptability or versatility
If separate differential receivers and single ended receivers are handled separately in circuit designs, then both receiver types can be supported, but the chip area consumed increases significantly
Solution Approach 1:
The patent designs a universal receiver architecture that can function as both a differential receiver and a single-ended receiver using the same hardware components. The level selection logic enables the same differential receiver circuit to handle both receiver types by adjusting the voltage levels and enabling/disabling specific paths. This multi-functional design eliminates the need for separate dedicated circuits for differential and single-ended reception, significantly reducing chip area while maintaining full adaptability.
3Adaptability or versatility
If a 1.8 V receiver circuit is directly connected to handle high voltage domain I/O signals in a range of 0V to 3.6 V, then the circuit can receive high voltage signals, but the amplifier saturates and cannot reliably receive signals above a common mode of 1.8 volts
Solution Approach 1:
The patent segments the voltage handling function into two distinct domains: a high voltage domain (3.3V) for I/O interface and a low voltage domain (1.8V) for internal receiver operation. The level selection logic and voltage translation mechanism divide the signal path so that high voltage signals are received at the I/O interface, translated to appropriate voltage levels, and then processed by the 1.8V receiver circuitry. This segmentation prevents direct exposure of the 1.8V amplifiers to high voltage signals that would cause saturation, while still enabling reception of the full high voltage signal range.
Data Source
AI summary
A high voltage tolerant single ended receiver circuit includes a voltage divider that is operative to divide in half single ended input signals that are greater than the threshold voltages of the voltage divider. A pass gate circuit is operative to receive single ended signals that are below the threshold voltages of the voltage divider. Output from the voltage divider is coupled to a first input of a modified Schmitt trigger circuit to control a high threshold level of the Schmitt trigger circuit. Output from the pass gate circuit is coupled to a second input of the modified Schmitt trigger circuit to control a low threshold level of the Schmitt trigger circuit.