Single-Ended Chip-to-Chip Link With Self-Referenced Receivers
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Solution Overview
Problem
In computing systems, data transmission between agents and endpoints on different dies faces challenges due to power supply variations and cross-coupling capacitance, leading to signal latency and corruption, as the reference voltage at the receiver does not accurately represent the power supply used at the transmitter.
Innovation Solution
A computing system design that uses multiple lanes for data transmission, where each receiver has a termination resistor connected to an integrating capacitor providing a reference voltage, and data words are mapped to code words to maintain a constant voltage, with control logic in the source and destination converting between the two to mitigate signal variations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If a reference signal is generated and sent to multiple receivers, then the receivers can reconstruct the received input signal, but power supply variations and cross-coupling capacitance cause variations in the transported signals that are not experienced by the reference voltage, leading to increased latency or data corruption
Solution Approach 1:
An integrating capacitor is introduced as an intermediary element that couples the transported data signals to the reference voltage generation. The capacitor integrates the signal currents from multiple termination resistors to generate a common-mode reference voltage that inherently tracks power supply variations, thereby mediating between the transported signals and the reference voltage to eliminate mismatches
Solution Approach 2:
The integrating capacitor creates a feedback mechanism where the reference voltage is dynamically adjusted based on the actual signal currents being transported. The capacitor integrates the current from the termination resistors, causing the reference voltage to automatically track and compensate for power supply variations and signal integrity issues in real-time
2Device complexity
If data words are transported directly on the multiple lanes, then the transmission is simple, but power supply variations and cross-coupling capacitance cause signal variations leading to data corruption
Solution Approach 1:
The integrating capacitor serves as an intermediary that indirectly couples the transported data signals to the reference voltage. Rather than directly sensing each signal, the capacitor integrates the cumulative effect of all signal currents through the termination resistors, providing a robust reference voltage that compensates for signal variations without requiring complex direct monitoring circuitry
3Device complexity
If the reference voltage is generated independently at the receiver, then the receiver circuitry is simple, but the reference voltage does not track the power supply variations at the transmitter, causing signal reconstruction errors
Solution Approach 1:
The integrating capacitor creates a feedback loop where the reference voltage is continuously adjusted based on the actual signal currents present on the transmission lanes. The capacitor integrates these currents, causing the reference voltage to automatically track transmitter power supply variations and signal integrity changes, thereby maintaining accurate signal reconstruction without complex independent regulation circuitry
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach ensures efficient data transmission by maintaining a constant reference voltage, reducing signal degradation and data corruption, and allowing for reliable reconstruction of data words at the destination.
Implementation Method 1
Each of the receivers in the destination has a respective termination resistor connected to a single integrating capacitor. The integrating capacitor provides a reference voltage to the plurality of receivers.
Data Source
AI summary
A system and method for efficiently transporting data in a computing system are contemplated. In various embodiments, a computing system includes a source, a destination and multiple lanes between them for transporting data. Multiple receivers in the destination has a respective termination resistor connected to a single integrating capacitor, which provides a reference voltage to the multiple receivers. The receivers reconstruct the received data by comparing the corresponding input signals to the reference voltage. The source includes a table storing code words. The source maps a generated data word to a code word, which is sent to the destination. The destination maps the received code word to the data word. The values of the code words are selected to maintain a nearly same number of Boolean ones on the multiple lanes over time as a number of Boolean zeroes.