Single Ended Memory Device Dynamic Reference Tracking
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Solution Overview
Problem
Conventional single-ended SRAM bit cells, such as the 2P-8T bit cell, face issues with read failure due to the reference current not dynamically reflecting changes in discharging and leakage currents across varying voltage levels, leading to incorrect differentiation of logical states.
Innovation Solution
A memory architecture with a reference circuit coupled to each bit cell, featuring transistors identical to the read driver and read transistors, which dynamically tracks the discharging and leakage currents, ensuring the reference current remains between these current levels even at different voltage operations, thus preventing read failures.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If a conventional single-ended SRAM bit cell uses a fixed reference current, then the circuit complexity is reduced, but read failures occur because the reference current does not dynamically reflect changes in discharging and leakage currents across varying voltage levels
Solution Approach 1:
The reference circuit dynamically adjusts the reference current based on the actual discharging and leakage currents of the bit cell. The track transistors continuously track the voltage levels and current characteristics, allowing the reference current to adapt to varying operating conditions and voltage levels, thereby preventing read failures while maintaining reasonable circuit complexity
Solution Approach 2:
The reference circuit incorporates feedback mechanisms where the discharging current and leakage current from the bit cell are fed back to the track transistors. This feedback loop enables the reference current to self-adjust and remain accurate across different voltage levels, resolving the contradiction between simple fixed reference circuits and reliable read operations
2Reliability
If the reference current is dynamically tracked to prevent read failures, then read operation reliability is improved, but the device complexity increases due to additional track transistors and reference circuits
Solution Approach 1:
The track transistors serve multiple functions: they track the discharging current, track the leakage current, and generate the reference current simultaneously. This multi-functionality reduces the need for separate dedicated circuits for each function, thereby limiting the increase in device complexity while achieving reliable read operations
Solution Approach 2:
The reference circuit is merged with the bit cell structure, sharing common transistors and circuit elements. The track transistors are integrated into the existing bit cell layout, combining the storage function and reference generation function in a unified structure, which minimizes the overall complexity increase
3Measurement precision
If transistors identical to read driver and read transistors are used in the reference circuit, then measurement precision of current levels is improved, but manufacturing precision requirements increase
Solution Approach 1:
The reference circuit uses transistors that are identical or matched to the read driver and read transistors in terms of size, structure, and electrical characteristics. This homogeneity ensures that the track transistors accurately replicate the current characteristics of the bit cell transistors, improving measurement precision while the matching is achieved through standard manufacturing processes
Data Source
AI summary
A memory device includes a memory cell that is configured to store a data bit, comprising at least one read transistor that is configured to form either a discharging path or a leakage path when the data bit is read; a conductive line coupled to the read transistor; and at least a first track transistor, coupled to the conductive line, and configured to provide a first current signal having a first current level that tracks a second current level of a second current signal, wherein the second current signal is provided when either one of the discharging and leakage paths is formed, and wherein the first the second current signals are used to determine a logical state of the data bit.