Single-Ended Chip Links With Adaptive Reference-Voltage Equalization
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Solution Overview
Problem
High-speed single-ended chip-to-chip wireline communication faces issues such as inter-symbol interference, low-pass characteristics of board traces, and voltage level loss due to DC resistance, leading to degraded edge-rate and increased bit error rates, which existing equalization techniques like pre-emphasis and analog filter-based methods fail to adequately address.
Innovation Solution
The implementation of a method using a plurality of voltage dividers coupled to provide a reference voltage, adjusted based on previously received data, to enhance communication by improving voltage margins during transmission of 'lonely' 0s and 1s, with a controller selectively activating the dividers to adjust the reference voltage accordingly.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If high-speed single-ended signaling is used, then communication speed is improved, but inter-symbol interference increases due to premature switching before voltage settles
Solution Approach 1:
The receiver stores previously received data in a history buffer and uses this historical information to predict and compensate for voltage level deviations before they affect current bit detection. By performing equalization based on past data patterns, the system prepares correction factors in advance, allowing high-speed operation without sacrificing signal integrity.
Solution Approach 2:
The system uses previously received data as feedback to adjust the reference voltage dynamically. The controller analyzes the history buffer contents and modifies the reference voltage accordingly, creating a closed-loop system that continuously compensates for inter-symbol interference effects, thereby maintaining reliable communication at high speeds.
2Speed
If higher frequency components are used to achieve faster edge-rate, then communication performance is improved, but losses increase due to low-pass characteristics of board traces
Solution Approach 1:
The patent replaces traditional analog filter-based equalization with a digital signal processing approach using a history buffer and controller. Instead of using complex analog circuits to compensate for frequency-dependent losses, the system uses digital logic to analyze past data patterns and adjust the reference voltage, thereby mitigating the effects of low-pass trace characteristics without requiring analog filters.
3Length of stationary object
If DC resistance of long board traces is present, then voltage level loss increases, but communication distance must be maintained
Solution Approach 1:
The system dynamically changes the reference voltage parameter based on the detected data patterns in the history buffer. When certain patterns (such as sequences of identical bits) are detected that are known to cause voltage level deviations due to DC resistance effects, the controller adjusts the reference voltage to compensate, thereby maintaining accurate bit detection despite voltage losses in long traces.
4Reliability
If driver-side pre-emphasis is used to mitigate ISI, then signal quality is improved, but switching noise on driver power supply increases
Solution Approach 1:
Instead of applying pre-emphasis at the driver side (transmitter), the patent inverts the approach by implementing equalization at the receiver side. The receiver uses a history buffer to detect patterns causing ISI and adjusts its reference voltage accordingly, thereby mitigating signal quality issues without requiring the driver to increase switching activity, thus avoiding additional switching noise on the power supply.
5Reliability
If traditional receiver-side equalization using analog filters is used, then signal equalization is achieved, but implementation difficulty in CMOS increases
Solution Approach 1:
The patent replaces complex analog filter circuits with a digital implementation using a history buffer and controller logic that can be easily integrated into CMOS technology. By using digital storage elements and logic circuits instead of analog components, the system achieves signal equalization with standard CMOS processes, significantly reducing implementation complexity while maintaining equalization effectiveness.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach effectively improves voltage margins and reduces bit error rates, enhancing the performance of single-ended chip-to-chip communication systems by dynamically adjusting the reference voltage in response to data patterns, thereby mitigating the effects of inter-symbol interference and voltage losses.
Implementation Method 1
providing a plurality of voltage dividers. The plurality of voltage dividers may be coupled to each other to provide a reference voltage to the receiver device
Data Source
AI summary
Disclosed are novel methods and apparatus for efficiently providing equalization in single-ended chip-to-chip communication. In an embodiment, a method of adjusting signal levels to provide improved communication between a sender device and a receiver device is disclosed. The method includes providing a plurality of voltage dividers. The plurality of voltage dividers may be coupled to each other to provide a reference voltage to the receiver device. The method further includes providing a storage device to store previously received data by the receiver device and providing a controller to selectively activate the plurality of voltage dividers.