Single-Ended SAR ADC Dual-DAC Benchmarking for Accurate Output Codes
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Solution Overview
Problem
Single-ended SAR ADCs suffer from inadequate comparison benchmarks due to a lack of clear voltage source, leading to inaccurate output codes and inferior performance compared to differential SAR ADCs.
Innovation Solution
A single-ended SAR ADC design that incorporates two digital-to-analog converters (DACs), a comparator, and a SAR controller, where capacitors in each DAC are connected to reference voltages to generate a self-based comparison benchmark through charge redistribution, allowing the SAR controller to control switching based on comparator outputs to produce accurate output codes.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If a single-ended SAR ADC uses a conventional single voltage source, then the circuit complexity is reduced and power dissipation is lowered, but the comparison benchmark becomes inadequate and output code accuracy deteriorates
Solution Approach 1:
The patent divides the single voltage source into two separate voltage sources (first voltage source and second voltage source). The first DAC uses the first voltage source while the second DAC uses the second voltage source. This segmentation allows each DAC to have an independent reference, enabling accurate comparison benchmark generation without increasing overall circuit complexity significantly.
Solution Approach 2:
The patent introduces a third voltage source as an intermediary reference voltage source that is coupled to a reference node. This intermediary reference serves as a common reference point for both DACs, allowing them to generate accurate comparison benchmarks while maintaining single-ended operation. The intermediary reference voltage mediates between the two separate voltage sources.
2Use of energy by moving object
If a single-ended SAR ADC uses a conventional single voltage source, then power dissipation is reduced, but the comparison benchmark becomes inadequate leading to inferior performance
Solution Approach 1:
The patent segments the power supply into two independent voltage sources, each powering one DAC. This allows for independent optimization of power consumption for each conversion path while maintaining reliable performance through accurate benchmark comparison. The segmented power supply reduces overall power dissipation compared to a high-power differential architecture.
Solution Approach 2:
The intermediary reference voltage source acts as a mediator that enables reliable comparison between the two DAC outputs without requiring high power consumption. It provides a stable reference that ensures accurate output code generation while maintaining energy efficiency characteristic of single-ended architectures.
3Ease of operation
If a single-ended SAR ADC uses a conventional single voltage source, then the ADC driver requirement is simplified, but the comparison benchmark lacks clarity resulting in inaccurate output
Solution Approach 1:
The patent segments the reference voltage function into two separate voltage sources, each dedicated to one DAC. This segmentation maintains the simplicity of single-ended operation (ease of operation) while providing clear, distinct comparison benchmarks for accurate output code generation. Each DAC has its own clear voltage reference.
Solution Approach 2:
The intermediary reference voltage source serves as a mediator that provides a common reference point, enabling clear comparison benchmarks without complicating the ADC driver requirements. It allows both DACs to operate independently with clear references while maintaining compatibility with simple single-ended drivers.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This design enhances the comparison benchmarking capability of single-ended SAR ADCs, improving output code accuracy and performance by enabling self-based charge redistribution and accurate bit generation, thereby overcoming the limitations of conventional single-ended ADCs.
Implementation Method 1
capacitors in each DAC are connected to reference voltages to generate a self-based comparison benchmark through charge redistribution
Data Source
AI summary
A single-ended successive approximation register (SAR) analog-to-digital converter (ADC) includes a first digital-to-analog converter (DAC) having a first capacitor associated with a most significant bit (MSB) of the output code, and a second capacitor associated with other bit or bits of the output code; and a second DAC having a first capacitor associated with a MSB of the output code, and a second capacitor associated with other bit or bits of the output code. A bottom plate of the first capacitor of the second DAC is connected to a negative reference voltage in all phases.