Single-Ended SRAM Cross-Point Write Operation
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Solution Overview
Problem
Conventional single-ended SRAMs face challenges in reducing leak current and increasing noise margin due to the requirement for sufficient channel aspect ratio, which increases circuit area and fabrication costs.
Innovation Solution
Incorporating a third switch in the memory cell that allows for controlled data transfer and leakage path isolation during writing and reading operations, reducing current leakage and enhancing noise margin by managing data transfer through word-line signals and control signals.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the channel aspect ratio of transistor M5 is increased to provide sufficient current driving capacity for single-ended writing operation, then the writing capability is improved, but the circuit area increases and fabrication cost increases
Solution Approach 1:
The writing operation is segmented into two independent paths: one for writing '0' data through transistor M5, and another for writing '1' data through transistor M6. This segmentation allows each transistor to have optimized, smaller channel aspect ratios while collectively achieving full writing capability through the dual-path architecture.
Solution Approach 2:
Transistors M5 and M6 are given dual functions: M5 handles both reading (original path) and writing '0' (new path), while M6 handles writing '1'. This multi-functionality eliminates the need for a dedicated writing transistor, reducing overall circuit area while maintaining writing capability.
2Reliability
If the channel aspect ratio of transistor M5 is increased to provide sufficient current driving capacity, then the noise margin is improved, but the circuit area increases
Solution Approach 1:
The noise margin improvement is segmented between two transistors M5 and M6, each contributing to the overall noise immunity. By distributing the current driving requirement across two transistors with moderate aspect ratios, the patent achieves sufficient noise margin without requiring one transistor to have an excessively large area.
3Area of stationary object
If conventional single-ended SRAM structure is used, then the circuit area is reduced, but the leak current increases due to insufficient control over data transfer paths
Solution Approach 1:
The patent dynamically controls the conduction state of transistors M5 and M6 through word-line signals (WWL and WRL). During writing operations, the appropriate transistor is activated; during non-writing operations, both are deactivated. This dynamic control eliminates static leakage paths while maintaining compact circuit area.
Solution Approach 2:
The bit-line transistors M5 and M6 act as intermediaries between the data-latching unit and the bit-lines. They mediate data transfer only when needed, blocking leakage paths when inactive. This intermediary control mechanism reduces leak current without requiring additional isolation structures that would increase area.
Data Source
AI summary
A single-ended SRAM including at least one memory cell and a third switch is provided. The memory cell includes a data-latching unit, a first switch, a second switch and a data-transferring unit. The data-latching unit is configured for latching the received input data and provides a storage data and the inverse data of the storage data. The first switch transfers a reference data to the data-latching unit according to a first word-line signal. The second switch transfers the reference data to the data-latching unit according to a second word-line signal. The data-transferring unit decides whether or not to transfer the reference data to the bit-line according to the storage data and a control signal. The third switch receives the reference data and the control signal and transfers the reference data to the first switch, the second switch and the data-transferring unit according to the control signal.