Single FEC Decoder Control for DVB-T2 Receive Data Flow
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Solution Overview
Problem
DVB-T2 receivers face challenges in efficiently processing asynchronous data and control information, leading to potential memory overflow and increased power consumption due to the need for separate FEC decoders for data and control signals, which can interrupt ongoing decoding processes.
Innovation Solution
Implementing control logic to prioritize processing of control information using a single FEC decoder, coupled with frequency and time deinterleavers, and a dejitter buffer with programmable memory management to schedule FEC outputs and prevent buffer overflows, allowing for efficient decoding of data and control signals without interrupting ongoing processes.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If separate FEC decoders are used for data and control signals, then processing reliability is improved, but device complexity and power consumption increase
Solution Approach 1:
The patent combines data FEC decoder and control signal FEC decoder into a single shared FEC decoder unit. The control logic dynamically allocates the decoder to process either data or control signals based on timing requirements, eliminating the need for separate decoder hardware while maintaining processing reliability through prioritized access control.
Solution Approach 2:
The FEC decoder is designed as a universal unit that can perform both data decoding and control signal decoding functions. The decoder responds to control signals that direct it to process different types of information (data PLPs or Common PLPs) using the same decoding hardware, achieving multi-functionality without requiring duplicate decoder instances.
2Reliability
If separate FEC decoders are used for data and control signals, then processing reliability is improved, but power consumption increases
Solution Approach 1:
The patent combines data FEC decoder and control signal FEC decoder into a single shared FEC decoder unit. The control logic dynamically allocates the decoder to process either data or control signals based on timing requirements, eliminating the need for separate decoder hardware while maintaining processing reliability through prioritized access control.
Solution Approach 2:
The system uses self-service mechanisms where the decoder automatically responds to control signals indicating whether to process data or control information. The control logic monitors buffer status and autonomously directs the decoder to the appropriate task without external intervention, optimizing power usage by activating the decoder only when needed.
3Productivity
If control information is prioritized in processing, then productivity is improved, but manufacturing precision deteriorates
Solution Approach 1:
The system performs preliminary actions by pre-buffering control signals and data in separate buffers before decoding. The control logic提前 prepares control information and directs the decoder to process it at the appropriate time, ensuring that prioritization does not compromise the accuracy of either data or control signal decoding through proper timing and buffer management.
4Device complexity
If a single FEC decoder is used, then device complexity is reduced, but reliability deteriorates due to potential interruptions
Solution Approach 1:
The patent introduces control logic as an intermediary between the data source and the shared FEC decoder. This mediator monitors buffer status, determines processing priorities, and directs the decoder to appropriate tasks through control signals. The intermediary ensures that switching between data and control signal processing does not compromise reliability by maintaining proper timing and preventing data loss.
5Reliability
If memory buffering is increased to prevent overflow, then reliability is improved, but device complexity and cost increase
Solution Approach 1:
The system employs dynamic buffer management where the control logic continuously monitors buffer status and adjusts processing rates accordingly. When buffers approach capacity thresholds, the control logic temporarily redirects the decoder to process control signals instead of data, dynamically balancing the load and preventing overflow without requiring excessively large fixed-size buffers.
Data Source
AI summary
Data flow control in a television receiver controls the output of the frequency deinterleaver (FDI) and the time deinterleaver (TDI) to prioritize processing control information having transmission parameters needed for processing data, thereby facilitating use of one FEC decoder.