Single-FET PUF Screening With Comparator Offset Margins
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Existing single FET compare PUF circuits are application-dependent and not flexible with changing field conditions, lacking efficiency and effectiveness in defining and screening transistor pairs for PUF challenge and response word generation.
Innovation Solution
A method and circuit utilizing a low-offset dynamic comparator to select and store FET pairs with suitable voltage offsets, discarding those below a margin threshold and using only stable pairs for PUF response generation, with adjustable margin thresholds without requiring redesign or calibration.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If single FET compare PUF circuits use built-in comparator offset devices with bit-flip signal to determine unstable FET pair combinations, then the PUF function can be implemented, but the circuit becomes application-dependent and not flexible with changing field conditions
Solution Approach 1:
The patent applies preliminary action by performing FET pair screening and characterization before the PUF circuit is deployed in the field. During manufacturing or initialization, all possible FET pairs are tested to determine their voltage offsets and stability characteristics. The results are stored in a lookup table or database, so that when the PUF circuit needs to operate under different field conditions, pre-validated FET pairs can be selected without requiring complex real-time adjustment circuitry. This resolves the contradiction by making the circuit simple while achieving adaptability through pre-computed data.
2Reliability
If all FET pairs are used for PUF response generation without screening, then the circuit operation is simplified, but unstable FET pairs reduce the reliability and effectiveness of PUF challenge and response word generation
Solution Approach 1:
The patent implements preliminary screening of FET pairs during manufacturing or initialization to identify stable pairs with appropriate voltage offsets. Each FET pair is characterized by measuring its voltage offset, and pairs that meet stability criteria are marked for use in PUF operations. This pre-screening eliminates unreliable FET pairs before deployment, ensuring high PUF response generation reliability without requiring complex real-time validation during operation. The screening complexity is paid once during setup, not continuously during operation.
Solution Approach 2:
The patent applies self-service by enabling the PUF circuit to automatically select appropriate FET pairs based on pre-stored characterization data. When a challenge input is received, the control logic automatically queries the lookup table to identify suitable FET pairs and routes the challenge to the appropriate pair, without requiring external intervention or complex decision-making circuitry. This automation maintains high reliability while keeping the operational complexity low.
3Adaptability or versatility
If margin threshold value is fixed during design, then the circuit design is simplified, but it cannot adapt to varying application needs without redesign or calibration
Solution Approach 1:
The patent applies preliminary action by computing and storing the voltage offset characteristics of all FET pairs during manufacturing, before the circuit is deployed. A lookup table is populated with the voltage offset values for each FET pair, along with indicators of their stability and suitability for PUF operations. During operation, the control logic can query this pre-computed data and select FET pairs that meet the required margin threshold for any given application. This allows the same physical circuit to adapt to different application requirements by simply changing which pre-characterized FET pairs are selected, without requiring physical redesign or recalibration.
Data Source
AI summary
A screening method and circuit for implementing a Physically Unclonable Function (PUF), and a design structure on which the subject circuit resides are provided. A plurality of field effect transistors (FETs) is coupled to a low-offset dynamic comparator and is respectively selected to provide a plurality of FET pairs. For each FET pair, a voltage offset to obtain a comparator output transition is identified and recorded. The recorded voltage offset for each FET pair is compared with a margin threshold value. Each FET pair having an identified voltage offset less than the margin threshold value is discarded or disabled for PUF response generation use.