Single-Fin FinFET Structure for Lower Parasitic Capacitance

Solution Overview

Problem

Integrated circuits in mobile applications face stringent power requirements, and existing methods for power reduction in single-fin finFET structures are limited, particularly in increasing transistor density while minimizing leakage current and parasitic capacitances.

Innovation Solution

A method involving fin height and source/drain height reduction in single-fin finFET structures is employed, utilizing insulating fins, sacrificial gate structures, and epitaxial stacks to minimize parasitic capacitances and leakage current, including etch processes and material deposition to form metal gate structures.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Productivity

If fin height is increased to increase transistor density, then device integration density is improved, but parasitic capacitance increases and power consumption increases

Engineering Contradiction:

Improvetransistor densityVSAvoidpower consumption

Core Design Contradiction:

ProductivityVSUse of energy by moving object

Solution Approach 1:

The fin structure is segmented into multiple fins within a single transistor device, allowing increased transistor density without proportionally increasing parasitic capacitance per transistor. Each fin acts as an independent current path, enabling parallel conduction channels that improve density while distributing the parasitic capacitance load across multiple smaller structures rather than one large structure

Inventive Principle:

Principle #1Segmentation

Solution Approach 2:

The invention transitions from planar 2D transistor structures to vertical 3D finFET structures by extending the active channel into the vertical dimension. This dimensional change allows increased effective channel width and transistor density without proportionally increasing the parasitic capacitance footprint on the substrate, as the capacitance is distributed along the vertical fin structure rather than concentrated in a planar layout

Inventive Principle:

Principle #17Another dimension (Dimensionality change)

2Productivity

If fin height is increased to increase transistor density, then device integration density is improved, but leakage current increases

Engineering Contradiction:

Improvetransistor densityVSAvoidleakage current

Core Design Contradiction:

ProductivityVSLoss of energy

Solution Approach 1:

The fin structure is segmented into multiple fins within a single transistor device, allowing increased transistor density without proportionally increasing parasitic capacitance per transistor. Each fin acts as an independent current path, enabling parallel conduction channels that improve density while distributing the parasitic capacitance load across multiple smaller structures rather than one large structure

Inventive Principle:

Principle #1Segmentation

Solution Approach 2:

The invention transitions from planar 2D transistor structures to vertical 3D finFET structures by extending the active channel into the vertical dimension. This dimensional change allows increased effective channel width and transistor density without proportionally increasing the parasitic capacitance footprint on the substrate, as the capacitance is distributed along the vertical fin structure rather than concentrated in a planar layout

Inventive Principle:

Principle #17Another dimension (Dimensionality change)

3Use of energy by moving object

If conventional power reduction methods are used in single-fin finFET structures, then some power reduction is achieved, but the methods are limited and cannot simultaneously increase transistor density while minimizing leakage and parasitic capacitance

Engineering Contradiction:

Improvepower consumptionVSAvoidtransistor density

Core Design Contradiction:

Use of energy by moving objectVSProductivity

Solution Approach 1:

The fin structure is segmented into multiple fins within a single transistor device, allowing increased transistor density without proportionally increasing parasitic capacitance per transistor. Each fin acts as an independent current path, enabling parallel conduction channels that improve density while distributing the parasitic capacitance load across multiple smaller structures rather than one large structure

Inventive Principle:

Principle #1Segmentation

Solution Approach 2:

The invention transitions from planar 2D transistor structures to vertical 3D finFET structures by extending the active channel into the vertical dimension. This dimensional change allows increased effective channel width and transistor density without proportionally increasing the parasitic capacitance footprint on the substrate, as the capacitance is distributed along the vertical fin structure rather than concentrated in a planar layout

Inventive Principle:

Principle #17Another dimension (Dimensionality change)

Data Source

PatentUS12527064B2Power reduction in finFET structures

Publication Date: 2026.01.13 TAIWAN SEMICONDUCTOR MANUFACTURING CO LTD

AI summary

The present disclosure describes a method to reduce power consumption in a fin structure. For example, the method includes forming a first and a second semiconductor fins on a substrate with different heights. The method also includes forming insulating fins between and adjacent to the first and the second semiconductor fins. Further, the method includes forming a first and second epitaxial stacks with different heights on each of the first and second semiconductor fins.