Single-Gate Delay Line for DLL Duty Cycle Symmetry
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Solution Overview
Problem
Conventional delay lines in delay lock loops suffer from non-linearity and duty cycle symmetry issues due to the use of two inverting gates in each delay stage, leading to excessive power consumption and limited adjustability, which affects the performance of phase mixers and clock signal synchronization.
Innovation Solution
A delay line with single NAND gates in each stage, combined with a phase inverter to ensure equal propagation delay for both rising and falling edges, reducing the coarse step size and improving phase mixer linearity by using a phase inverter to invert only the OddOut signal, thus minimizing duty cycle skew and enhancing interpolation range.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Stability of the object's composition
If two inverting gates are used in each delay stage, then duty cycle symmetry is improved, but power consumption increases and device complexity increases
Solution Approach 1:
The patent removes one inverting gate from each delay stage, extracting only the necessary delay function while eliminating the redundant inverting operation. This reduces power consumption and device complexity while maintaining duty cycle symmetry through the phase inverter that compensates for the single gate's asymmetry.
Solution Approach 2:
The patent intentionally introduces asymmetry by using a single NAND gate instead of two symmetric inverting gates, then compensates for this asymmetry using a phase inverter. This asymmetric approach reduces power consumption while the phase inverter restores the required duty cycle symmetry.
2Stability of the object's composition
If two inverting gates are used in each delay stage, then duty cycle symmetry is improved, but device complexity increases
Solution Approach 1:
The patent extracts only the essential delay function from the two-gate configuration, removing one gate to reduce device complexity. The phase inverter is introduced to compensate for the reduced symmetry, achieving a net reduction in overall device complexity while maintaining performance.
3Device complexity
If coarse delay steps are used, then device complexity is reduced, but measurement precision deteriorates
Solution Approach 1:
The patent segments the delay adjustment into two independent parts: a coarse delay line with fewer, larger steps for overall delay adjustment, and a fine delay line with smaller steps for precise phase synchronization. This segmentation allows the system to achieve high measurement precision without requiring an excessively complex single-stage delay line.
Solution Approach 2:
The patent implements dynamic adjustment by allowing the system to switch between coarse and fine delay modes. The coarse delay provides rapid, large-step adjustment while the fine delay provides precise, small-step adjustment, creating a dynamic system that adapts its resolution based on the synchronization requirements.
4Measurement precision
If fine delay steps are used, then measurement precision is improved, but device complexity increases
Solution Approach 1:
The patent divides the delay control function into two separate delay lines: one optimized for coarse adjustment and another for fine adjustment. This segmentation allows each line to be independently optimized, with the fine delay line providing high precision without requiring the entire system to be overly complex.
Data Source
AI summary
Locked loops, delay lines, delay circuits, and methods for delaying signals are disclosed. An example delay circuit includes a delay line including a plurality of delay stages, each delay stage having an input and further having a single inverting delay device, and also includes a two-phase exit tree coupled to the delay line and configured to provide first and second output clock signals responsive to clock signals from inputs of the delay stages of the plurality of delay stages. Another example delay circuit includes a delay line configured to provide a plurality of delayed clock signals, each of the delayed clock signals having a delay relative to a previous delayed clock signal equal to a delay of a single inverting delay device. The example delay circuit also includes a two-phase exit tree configured to provide first and second output clock signals responsive to the delayed clock signals.