Single Gate Oxide I/O Circuit with Dynamic Gate Bias Control
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Solution Overview
Problem
Conventional dual gate oxide technology for I/O circuits requires separate masks, increasing manufacturing costs and decreasing product yield due to the need for high voltage stress tolerance in systems operating at different voltage levels.
Innovation Solution
A single gate oxide I/O circuit design utilizing PMOS and NMOS transistors with a switch module and feedback circuit to control gate biases, ensuring voltages across transistors remain within a predetermined range, thereby preventing damage from high voltage stress.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If dual gate oxide technology is used to withstand high voltage inputs, then high voltage stress tolerance is improved, but manufacturing complexity increases due to requiring two separate sets of masks
Solution Approach 1:
The patent changes the electrical parameters (gate biases) of the MOS transistors dynamically through feedback control, rather than changing the physical structure (gate oxide thickness). By adjusting gate biases to keep voltages across transistor gates within a predetermined range, the circuit achieves high voltage stress tolerance using a single gate oxide layer, eliminating the need for dual gate oxide technology and its associated manufacturing complexity.
2Reliability
If dual gate oxide technology is used for high voltage tolerance, then reliability under high voltage is improved, but product yield decreases
Solution Approach 1:
The invention uses dynamic parameter adjustment (gate biases) rather than structural modification (different gate oxide thicknesses) to achieve high voltage tolerance. This approach allows all transistors to be fabricated with the same gate oxide layer using a single set of masks, thereby improving product yield rates while maintaining the ability to withstand high voltage inputs through feedback-controlled bias adjustment.
3Speed
If thinner gate oxide is used for lower voltage operation, then switching time and power consumption are reduced, but voltage breakdown occurs under high voltage conditions
Solution Approach 1:
The patent employs feedback control to monitor the voltage at the I/O pad and dynamically adjust the gate biases of the MOS transistors accordingly. When high voltage is detected, the feedback circuit modifies the gate biases to ensure that the voltage across each transistor's gate remains within the breakdown voltage limit, even when the I/O pad experiences voltages exceeding what the thin gate oxide could normally withstand. This allows the use of thin gate oxide for fast switching while preventing voltage breakdown through active control.
Solution Approach 2:
The feedback circuit performs preliminary anti-action by preemptively adjusting gate biases before voltage breakdown can occur. When high voltage conditions are detected at the I/O pad, the control mechanism modifies the gate biases in advance to prevent the voltage across transistor gates from exceeding breakdown levels, thereby protecting the thin gate oxide transistors from damage while maintaining their fast switching characteristics.
Data Source
AI summary
An I/O output circuit is disclosed for interfacing a first system operating at a first voltage with a second system operating at a second voltage higher than the first voltage. The I/O output circuit includes an output stage module having one or more PMOS transistors and one or more NMOS transistors for coupling with the second system. A switch module is coupled to the output stage module for selectively providing the PMOS and NMOS transistors with various gate biases. A feedback circuit is coupled between an I/O pad that couples the output stage module to the second system and the switch module for controlling the switch module to generate the gate biases in response to a voltage at the I/O pad, thereby ensuring voltages across gates of the PMOS and NMOS transistors to be within a predetermined range.