Single Gate Precharge Circuit Layout for Memory Devices
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Solution Overview
Problem
Existing memory devices face challenges in reducing the space occupied by sensing and precharge circuitry, which is substantial and has seen limited success in minimization efforts.
Innovation Solution
The memory device employs a configuration where a single conductive line is used to provide different voltages to both the N-sense amplifier and precharge circuit at different times, sharing transistors and diffusion regions to reduce circuit size and the number of conductive lines, allowing for a more compact layout.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If separate conductive lines are used for N-sense amplifier and precharge circuit, then each circuit can be independently controlled, but the number of conductive lines increases and space is consumed
Solution Approach 1:
The patent merges the control of N-sense amplifier and precharge circuit into a single conductive line by using a transmission gate that can be selectively activated. The transmission gate combines NMOS and PMOS transistors to pass both high and low voltage levels, enabling a single line to deliver different voltage states to different circuits at different times, thus reducing the number of conductive lines while maintaining independent control capability through temporal multiplexing.
Solution Approach 2:
The single conductive line is designed to serve multiple functions: it can provide voltage to the N-sense amplifier during sensing operations and provide voltage to the precharge circuit during precharge operations. The transmission gate acts as a universal switching element that routes the single voltage source to different destinations based on operational requirements, making the conductive line multi-functional rather than dedicated to a single circuit.
2Reliability
If multiple transistors are used in precharge circuit, then circuit functionality is achieved, but the number of transistor gates increases and layout space is consumed
Solution Approach 1:
The patent combines multiple transistor gates into a single shared gate structure. The transmission gate uses complementary NMOS and PMOS transistors with their gates controlled by complementary signals (EN and EN*), allowing a single physical gate structure to control multiple transistor operations. This merging reduces the total number of separate gates while maintaining the ability to independently control different circuit functions through complementary signal timing.
Solution Approach 2:
The single gate structure of the transmission gate serves multiple functions by controlling both the NMOS and PMOS transistors within it. When the enable signal is active, the transmission gate conducts; when inactive, it blocks. This universal gate controls voltage transmission to both the N-sense amplifier and precharge circuit at different times, reducing gate count while preserving full circuit functionality through temporal multiplexing.
Data Source
AI summary
Some embodiments include apparatus and methods using a first diffusion region, a second diffusion region, a third diffusion region, and a fourth diffusion region; a first channel region located between a portion of the first diffusion region and a portion of the third diffusion region; a second channel region located between the portion of the third diffusion region and a portion of the second diffusion region; a third channel region located between the portion of the second diffusion region and a portion of the fourth diffusion region; and a gate located over the first, second, and third channel regions. The first and second diffusion regions are located on a first side of the gate. The third and fourth diffusion regions are located on a second side of the gate opposite from the first side.