Single Gate Semiconductor Device With Shared Floating Gate
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Solution Overview
Problem
Existing nonvolatile memory integrated circuits with single gate memory cells, which include both a transistor and a capacitor, face challenges in achieving optimal doping configurations and well structures to enhance memory operations and programmability.
Innovation Solution
The semiconductor device incorporates multiple doping regions with specific doping types on both sides of the gate, including a shared floating gate connecting the transistor and capacitor, with epitaxial layers and spacers to define source and drain regions, allowing for improved control over memory operations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If multiple doping regions with opposite doping types are introduced on both sides of the gate, then short channel effects are improved and threshold voltage control is enhanced, but device complexity and manufacturing process difficulty increase
Solution Approach 1:
The patent applies local quality by introducing specific doping regions (first doping regions with first doping type, second doping regions with second doping type opposite to the first) at localized positions on both sides of the gate. These doping regions are positioned to overlap with source and drain regions, providing localized electrical property modification to control threshold voltage and improve short channel effects without requiring complex global structural changes.
Solution Approach 2:
The doping structure is segmented into multiple distinct regions: first doping regions, second doping regions, third doping regions, and fourth doping regions, each with specific doping types and positions. This segmentation allows independent optimization of each region's electrical characteristics, enabling precise control over the device's threshold voltage and short channel behavior while maintaining a manageable manufacturing process.
2Area of stationary object
If a shared floating gate connects both transistor and capacitor gate regions, then device area is reduced and integration is improved, but control precision over individual components decreases
Solution Approach 1:
The shared floating gate structure allows a single gate region to serve dual functions: controlling both the transistor channel and the capacitor. This multi-functional design reduces the total device area and improves integration density. The same floating gate structure enables both memory storage (via capacitor) and selection/control (via transistor) functions, achieving space efficiency without requiring separate gate structures.
3Manufacturing precision
If epitaxial layers and spacers are used to define source and drain regions, then manufacturing precision is improved, but process complexity and production time increase
Solution Approach 1:
The patent employs preliminary action by forming epitaxial layers and spacers before final source and drain region definition. The spacers are deposited and patterned in advance to serve as masks and alignment references for subsequent doping and etching steps. This preliminary structuring enables precise definition of source and drain regions while streamlining the overall manufacturing sequence, reducing the need for multiple iterative alignment steps.
Data Source
AI summary
A semiconductor device has a gate multiple doping regions on both sides of the gate. The gate can be shared by a transistor and a capacitor.