Single-Gate Vertical Transistor DRAM Cell for Tighter Pitch
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Solution Overview
Problem
Existing vertical transistors in 1T DRAM cells require two separate gate contacts to bias the transistor channel, which is cumbersome and occupies valuable space, especially as device pitch decreases, making it challenging to achieve efficient memory storage in smaller pitches.
Innovation Solution
A Vertical Field Effect Transistor (VFET) design with a single external gate contact that biases one channel side in accumulation and the other in inversion, using different materials for the channel sides and gate stacks to induce a threshold voltage difference, allowing for tighter pitch spacing and eliminating the need for a second gate contact.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If two separate gate contacts are used to bias the transistor channel in inversion and accumulation, then the transistor can be properly controlled for memory storage, but the device occupies more space and becomes cumbersome for small pitch devices
Solution Approach 1:
The patent merges two separate gate contacts into a single shared gate contact structure. The single gate contact is positioned to control both the first channel side (biased in inversion) and the second channel side (biased in accumulation), eliminating the need for two separate gate contacts and reducing device area while maintaining proper transistor control capability
Solution Approach 2:
The patent applies local quality by creating asymmetric channel sides with different material compositions or doping profiles. The first channel side is engineered to be biased in inversion while the second channel side is engineered to be biased in accumulation, allowing each region to have optimized local properties for its specific function under the control of a single gate contact
2Area of stationary object
If a single gate contact is used to bias both channel sides, then device spacing can be reduced, but it becomes difficult to bias one side in inversion and the other in accumulation simultaneously
Solution Approach 1:
The patent implements local quality by engineering the first channel side and second channel side with different material compositions, doping concentrations, or structural properties. This allows the single gate contact to induce opposite bias conditions (inversion on one side, accumulation on the other) by exploiting the local differences in electrical characteristics between the two channel sides
Solution Approach 2:
The patent employs asymmetry by designing the channel structure with non-uniform properties across the two channel sides. The first channel side may have different doping levels, material composition, or geometric dimensions compared to the second channel side, enabling differential bias control from a single gate contact and facilitating simultaneous inversion and accumulation states
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The VFET design enables efficient memory storage with a single gate contact, allowing for tighter device spacing and improved memory performance by inducing a significant threshold voltage difference between channel sides, facilitating the use of a single external gate contact to bias the channel sides oppositely.
Implementation Method 1
A gate bias (voltage) applied on the single external gate connection biases the first channel side in accumulation and biases the second channel side in inversion
Implementation Method 2
One of the channel ends forms a floating body region, i.e. a capacitance, used by the 1T DRAM
Data Source
AI summary
A Vertical Field Effect Transistor (VFET) and/or a one transistor dynamic random access memory 1T DRAM that has a substrate with a horizontal substrate surface, a source disposed on the horizontal substrate surface, a drain, and a channel. The channel has a channel top, a channel bottom, a first channel side, a second channel side, and two channel ends. The channel top is connected to the drain. The channel bottom is connected to the source. The channel is vertical and perpendicular to the substrate surface.A first gate stack interfaces with the first channel side and a second gate stack interfaces with the second channel side. A single external gate connection electrically connects the first gate stack and the second gate stack A gate bias (voltage) applied on the single external gate connection biases the first channel side in accumulation and biases the second channel side in inversion. The first gate stack is made of a first high-k dielectric layer and a first gate metal layer. The second gate stack is made of a second high-k dielectric layer and a second gate metal layer. The single external gate electrical connection is made to the first gate metal layer and the second gate metal layer. The first and second channel side can be made of the same or different materials. The first and second gate metal layer can be made of the same or different materials.One of the channel ends forms a floating body region, i.e. a capacitance, used by the 1T DRAM.