Single Hash Function for Collision-Free Cache Addressing
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Solution Overview
Problem
Existing caching systems face performance degradation due to collisions when compressing K-bit memory addresses to H_max bit cache addresses, as they often require multiple hash functions for different cache cell subsets, leading to increased complexity and resource usage.
Innovation Solution
A caching system utilizing a single hash function that compresses K-bit memory addresses to H_max bit cache addresses, with a logic circuit generating a cache address of length H_select to ensure distinct mappings and prevent collisions, allowing for perfect hashing across different cache cell subsets.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If multiple hash functions are used for different cache cell subsets, then collision-free hashing can be achieved for each application, but device complexity and resource requirements increase
Solution Approach 1:
A single hash function is designed to serve multiple applications with different cache cell subset requirements. The hash function generates H_max bit outputs that can be selectively truncated to H_select bits for different applications, eliminating the need for separate hash functions while maintaining collision-free performance across all applications.
Solution Approach 2:
The system changes the parameter H_select (number of cache cell bits) to accommodate different application requirements. By varying this parameter while using the same underlying hash function, the system adapts to different cache sizes and usage patterns without requiring multiple fixed hash functions.
2Device complexity
If a single hash function is used for all applications, then device complexity is reduced, but collision probability increases for specific cache cell subsets
Solution Approach 1:
The system extracts only the necessary H_select bits from the full H_max bit hash output for each application. This extraction approach allows the single hash function to serve multiple purposes while each application receives only the specific number of bits it needs, maintaining collision-free performance for each application's cache cell subset.
3Quantity of substance
If cache size is reduced from 1M to 100 cells, then resource requirements decrease, but collision frequency increases without perfect hashing
Solution Approach 1:
The same hash function and logic circuit system serves both large (1M cell) and small (100 cell) cache configurations. By adjusting H_select based on the cache size, the system maintains perfect hashing capability regardless of whether the cache contains 100 or 1,000,000 cells, eliminating collisions in both scenarios.
Data Source
AI summary
A caching system operative in conjunction with a memory and a cache, the caching system comprising a processor to use only a single hash function which compresses K bit memory addresses to H_max bit cache addresses, rather than using plural hash functions, to provide perfect hashing for each of plural applications which utilize plural respective subsets, of different sizes, from among 2{circumflex over ( )}H_max cells in the cache; and at least one logic circuit X which receives, as one of its input operands, an output, H_max bits in length, of the single hash function and which generates, as a logic circuit output, a cache address of length H_select to which at least one K-bit address is mapped where H_max<K, to ensure that input operands which differ only by H_select<=H_max bits, map to distinct hash values with no collisions.