Single-Inversion Pulse Flop Without Output Buffer Delay
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Solution Overview
Problem
As processor frequencies increase, the delay caused by clocked state elements grows, reducing the time available for 'useful work' and necessitating additional output buffers in complex circuits, which are costly and time-consuming to build and characterize.
Innovation Solution
The introduction of a 'pulse flop' with a single inversion delay, where the storage feedback loop is placed in parallel with the critical evaluation path, eliminating the need for output buffers and allowing standard cell library logic to replace them, thereby reducing delay and cost.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If traditional clocked state elements (flops) are used to store state at clock cycle boundaries, then state storage function is achieved, but delay grows to a larger percentage of clock cycle time, reducing time available for useful work
Solution Approach 1:
The patent segments the clock cycle into distinct phases: an evaluation phase where logic operations occur without clocking, and a brief sampling phase where state is captured. This segmentation allows the majority of the clock cycle to be dedicated to useful computational work rather than state storage overhead, directly addressing the time loss problem while maintaining reliable state storage functionality.
2Reliability
If many flops are present in a single logical path, then state storage capacity increases, but delay increases and output buffers are necessitated, increasing cost and complexity
Solution Approach 1:
The patent merges the state storage function with the logic evaluation path by using the same signal line for both purposes during the evaluation phase. The storage element samples the logic result directly at the end of the evaluation phase without requiring separate output buffers, thereby reducing device complexity while maintaining adequate state storage capacity through the phased operation approach.
Data Source
AI summary
A single inversion pulse flop includes a critical evaluation path with a single inverter and a storage feedback loop arranged in parallel with the critical evaluation path. The single inversion pulse flop incurs a single inversion delay and does not require an output buffer.