Single Lane Keccak Execution Circuitry for SHA-3 Latency Reduction
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Solution Overview
Problem
Current processor architectures face inefficiencies in executing Keccak instructions due to high latency associated with cross-lane data accesses, which hinders the performance of Secure Hash Algorithm (SHA-3) and Post-Quantum Cryptography (PQC) schemes, particularly in Keccak permutations.
Innovation Solution
Introduction of new Keccak instructions that utilize a single lane of multiple lane registers and execution circuits to accelerate complex bit manipulations and byte reordering, such as the SHA3-SL-PAR, SHA3-SL-TXR1, SHA3-SL-TXR2, SHA3-SL-PI, and SHA3-SL-CHI instructions, reducing latency and enabling parallel execution of Keccak permutations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If cross-lane data accesses are used in Keccak execution, then parallel processing capability is utilized, but latency increases significantly
Solution Approach 1:
The patent segments the Keccak execution into independent single-lane operations that can be sequentially executed within one lane, avoiding the need for cross-lane data accesses. Each Keccak permutation is broken down into discrete steps (theta, rho, pi, chi, iota) that operate independently within a single lane, eliminating latency while maintaining functional correctness.
Solution Approach 2:
Instead of using multiple lanes in parallel (the conventional approach), the patent inverts the approach by using a single lane to execute Keccak permutations sequentially. This inversion eliminates the cross-lane access latency problem while achieving comparable or better performance through optimized single-lane execution paths.
2Quantity of substance
If multiple lane registers are used for Keccak instructions, then data throughput increases, but access latency increases
Solution Approach 1:
The patent processes data in segmented single-lane portions rather than attempting to process entire multiple-lane registers simultaneously. By dividing the Keccak state into manageable single-lane segments and processing them sequentially, the patent maintains data throughput while eliminating the access latency associated with multiple-lane operations.
3Loss of time
If single lane execution is used for Keccak instructions, then latency is reduced to single cycle, but processing capacity decreases
Solution Approach 1:
The patent maintains continuous useful action by implementing optimized single-lane execution paths that process Keccak permutations without interruption. The single-lane approach is enhanced with specialized micro-operations and instruction fusion techniques that keep the execution unit continuously busy, compensating for the reduced parallel capacity with increased operational efficiency.
Solution Approach 2:
The patent changes operational parameters by optimizing the single-lane execution path with specialized instructions and micro-operations tailored for Keccak algorithms. This includes optimizing register allocation, instruction scheduling, and data flow within the single lane to maximize processing capacity despite the reduced parallelism.
Data Source
AI summary
Circuitry and methods for implementing one or more Keccak permutation instructions are described. In certain examples, a hardware processor (e.g., core) includes decoder circuitry to decode a first instruction into a decoded first instruction, the first instruction comprising identifiers of a first register to store a first word of Keccak state value, a second register to store a second word of Keccak state value and a third word of Keccak state value, and a third register to store a fourth word of Keccak state value and a fifth word of Keccak state value according to a SHA3 standard, and an opcode to indicate vector execution circuitry comprising a plurality of lanes is to use only a single lane of the plurality of lanes to perform a column parities operation of a theta step of a Keccak permutation according to the SHA3 standard to determine a computed parity value for an input of the first word of Keccak state value, the second word of Keccak state value, the third word of Keccak state value, the fourth word of Keccak state value, and the fifth word of Keccak state value, and store the computed parity value into an unused upper word of the first register; and the vector execution circuitry to execute the decoded first instruction according to the opcode.