Single Latch Data Circuit for MLC Flash Memory
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Solution Overview
Problem
The high transistor count in sense amplifier data latches of multiple level cell (MLC) flash memory devices increases the complexity and cost, necessitating a reduction in the number of transistors required for efficient data handling.
Innovation Solution
A single latch data circuit is implemented in MLC non-volatile memory devices, utilizing two inverters and three control transistors to manage data storage and retrieval, allowing for the handling of two bits per cell with reduced transistor count through innovative control signal management and read-modify-write techniques.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If multiple level cell (MLC) flash memory devices use traditional sense amplifier data latches, then data storage and retrieval capability is improved, but transistor count and circuit complexity increase
Solution Approach 1:
The patent merges the functionality of two separate latches into a single latch circuit. The single latch uses two inverters and three control transistors to handle two bits of data from MLC cells, consolidating what would traditionally require two separate latch circuits and their associated transistors. This merging reduces the overall transistor count while maintaining the capability to store and retrieve two bits of data.
Solution Approach 2:
The single latch circuit is designed to perform multiple functions: it can latch two different bits of data (DQ0 and DQ1) from MLC cells, support read-modify-write operations, and interface with sense amplifiers. By making the latch universal and multi-functional, the patent eliminates the need for separate dedicated latches for each bit line, thereby reducing transistor count while maintaining full data handling capability.
2Quantity of substance
If MLC memory devices increase memory density without adding cells, then memory capacity is improved, but the number of transistors per cell increases
Solution Approach 1:
The patent applies merging by combining the data path for two bits into a single latch structure. Instead of having separate latches for each bit that would increase transistor count proportionally, the single latch handles both bits using shared control transistors and inverters, thus achieving higher memory density without a proportional increase in transistors per cell.
Solution Approach 2:
The patent changes the operational parameters of the latch circuit by using control signals (such as /Q0 and /Q1) to selectively latch different bits at different times during read-modify-write operations. This temporal multiplexing of the latch functionality allows a single latch to handle multiple bits, reducing the transistor count required per cell while maintaining MLC density.
Data Source
AI summary
A single latch circuit is coupled to each bit line in a multiple level cell memory device to handle reading multiple data bits. The circuit is comprised of a latch having an inverted node and a non-inverted node. A first control transistor selectively couples the non-inverted node to a latch output. A second control transistor selectively couples the inverted node to the latch output. A reset transistor is coupled between the inverted node and circuit ground to selectively ground the circuit when the transistor is turned on.