Single Latch Page Buffer with Buffer RAM for Compact Multi-bit Flash Memory
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Solution Overview
Problem
Conventional non-volatile semiconductor memory devices, such as flash memory devices, face challenges in manufacturing compact and cost-effective multi-bit memory devices without complex patterning techniques, as they typically require double latch structures that occupy more space.
Innovation Solution
The implementation of a multi-bit non-volatile memory device with a page buffer having a single latch structure and a buffer RAM, where the page buffer stores the least significant bit (LSB) and intermediate program data, while the buffer RAM stores the most significant bit (MSB), allowing for a more compact design and improved performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If a double latch structure is used to store multi-bit data, then data storage capability is improved, but device area occupied increases
Solution Approach 1:
The patent divides the data storage function into two separate components: a single latch structure in the page buffer for storing LSB and intermediate program data, and a buffer RAM for storing MSB. This segmentation allows each component to be optimized independently, reducing the total area compared to a unified double latch structure while maintaining full data storage capability.
Solution Approach 2:
The patent introduces a buffer RAM as an intermediary storage component between the page buffer and memory cell array. The buffer RAM temporarily holds MSB data and intermediate program data, allowing the single latch structure to suffice in the page buffer, thereby reducing area occupation while preserving multi-bit data storage functionality.
2Area of stationary object
If a single latch structure is used in the page buffer, then device area is reduced, but data storage capacity decreases
Solution Approach 1:
The patent transitions from a two-dimensional expansion (adding more latch structures in the page buffer) to a three-dimensional storage architecture by introducing a separate buffer RAM component. This dimensional change allows MSB data to be stored externally, compensating for the reduced capacity of the single latch structure while maintaining compact page buffer area.
Solution Approach 2:
The buffer RAM serves multiple functions: storing MSB data, holding intermediate program data during programming operations, and acting as a temporary buffer during data transfer between the memory cell array and page buffer. This multi-functionality compensates for the single latch structure's limited capacity, maintaining overall data storage capability while reducing area.
Data Source
AI summary
A multi-bit non-volatile memory device is provided. The memory device includes a memory cell array including a plurality of memory cells. A page buffer is electrically coupled to the memory cell array. The page buffer includes a plurality of latches configured to store a first bit of multi-bit data to be written into or read out from one of the plurality of memory cells of the memory cell array. A buffer random access memory (RAM) is electrically coupled to the page buffer. The buffer RAM is configured to store a second bit of the multi-bit data to be written into or read out from one of the plurality of memory cells of the memory cell array. Related systems, memory cards and methods are also provided.