Single Latch Page Buffer for Multi-bit Flash Memory
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Solution Overview
Problem
Conventional non-volatile semiconductor memory devices, such as flash memory devices, face limitations in manufacturing compact and high-performance multi-bit memory devices without complex patterning techniques or new manufacturing processes.
Innovation Solution
The development of a multi-bit flash memory device with a single latch page buffer and buffer RAM, which allows for efficient programming of memory cells by storing and reloading data, enabling smaller device sizes and improved performance through optimized programming operations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If multiple latch structures are used to store multi-bit data, then data storage capacity is improved, but device area and complexity increase
Solution Approach 1:
The patent merges the functions of multiple latch structures into a single latch structure that can store multi-bit data (LSB and MSB) through clever circuit design. The single latch uses cross-coupled transistors and shared bit lines to accomplish what traditionally required separate latch circuits, thereby reducing device area while maintaining data storage capacity.
Solution Approach 2:
The single latch structure is designed to perform multiple functions: storing LSB data, storing MSB data, and enabling sequential read operations. By making the latch universal and multi-functional, the patent eliminates the need for separate latch structures for different data bits, thus reducing overall device complexity and area.
2Ease of operation
If multiple flip-flop circuits are used to store LSB and MSB separately, then data read/write operations are simplified, but device complexity and manufacturing difficulty increase
Solution Approach 1:
The patent segments the data read/write operation into sequential steps (first MSB then LSB) while using a single unified latch structure. This temporal segmentation allows complex multi-bit operations to be broken down into simpler sequential steps, maintaining ease of operation without requiring multiple parallel latch circuits that would increase device complexity.
Solution Approach 2:
The single latch structure dynamically switches between storing and accessing different data bits (LSB/MSB) based on operational phase. The circuit transitions between different functional states during read operations, allowing one static physical structure to perform multiple logical functions, thereby reducing device complexity while maintaining operational simplicity.
3Ease of manufacture
If conventional flash memory devices are used, then manufacturing is simpler, but device size and capacity are limited
Solution Approach 1:
The patent combines multiple data bit storage functions into a single latch structure, which directly reduces the overall device footprint. This merging approach maintains compatibility with conventional manufacturing processes while achieving higher data density and smaller device size, as the same manufacturing techniques can fabricate the integrated single-latch design.
Data Source
AI summary
Multi-bit flash memory devices are provided. The multi-bit flash memory device includes an array of memory cells and a page buffer block including page buffers. Each of the page buffers has a single latch structure and performs a write operation with respect to memory cells according to loaded data. A buffer random access memory (RAM) is configured to store program data provided from an external host device during a multi-bit program operation. Control logic is provided that is configured to control the page buffer block and the buffer RAM so that program data stored in the buffer RAM is reloaded into the page buffer block whenever data programmed before the multi-bit program operation is compared with data to be currently programmed. The control logic is configured to store data to be programmed next in the buffer RAM before the multi-bit program operation is completed.