Single-Layer Driving Circuit for Ultra-Narrow Bezel Displays
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Solution Overview
Problem
The high cost of the COF driving scheme for introducing Gate signals in liquid crystal panels limits the adoption of ultra-narrow bezel displays, as it requires complex bonding processes and increased production costs.
Innovation Solution
A driving circuit design where data lines and gate lines are disposed at the same layer, with source and gate drivers located above them, eliminating the need for via holes and reducing production costs through a single-layer thin film wiring design.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Shape
If the COF driving scheme is used to introduce Gate signals from the source side, then ultra-narrow bezel display is achieved, but the preparation cost increases
Solution Approach 1:
The patent merges the data lines and gate lines into the same layer structure, allowing both signal types to coexist in a single-layer thin film wiring design. This integration eliminates the need for separate layers and via holes, reducing manufacturing complexity and cost while maintaining the ultra-narrow bezel shape achieved by the COF driving scheme
2Reliability
If data lines and gate lines are disposed at different layers, then signal transmission is achieved, but via holes are required increasing complexity
Solution Approach 1:
The patent transitions from a multi-layer vertical arrangement to a single-layer planar arrangement by disposing both data lines and gate lines in the same layer. This dimensional change eliminates the need for via holes that would connect different layers, reducing device complexity while maintaining effective signal transmission through optimized in-plane routing
Data Source
AI summary
The present disclosure provides a driving circuit and a display device, where the driving circuit includes: data lines and gate lines disposed at a same layer; and a source driver and a gate driver located above the data lines and the gate lines, where the data lines are connected to the source driver, and the gate lines are connected to the gate driver.