Single-Layer Gate Nonvolatile Memory for SoC Fabrication
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Solution Overview
Problem
The complexity of fabrication processes increases when embedding nonvolatile memory devices with stacked gate structures alongside logic devices with single gate structures in a system on chip (SoC), leading to difficulties in simplifying the fabrication of semiconductor chips.
Innovation Solution
A nonvolatile memory device with a single-layer gate structure, including specific well regions, contact regions, and diodes, which allows for simplified fabrication and operation through the use of tunneling and coupling capacitors, enabling program, erase, and read operations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a stacked gate structure is used in nonvolatile memory devices, then the memory function is achieved, but the fabrication process complexity increases when embedding alongside logic devices with single gate structures
Solution Approach 1:
The patent extracts the inter-gate insulating layer and floating gate from the conventional stacked gate structure, retaining only the essential control gate layer. This simplified single-layer gate structure maintains the nonvolatile memory function while eliminating the fabrication complexity associated with multiple stacked layers, allowing seamless integration with logic devices using single gate structures in SoC applications.
2Reliability
If a stacked gate structure is used, then nonvolatile memory operation is enabled, but the number of fabrication process steps increases
Solution Approach 1:
The patent removes the floating gate and inter-gate insulating layer from the stacked gate structure, reducing the number of fabrication process steps. The remaining single-layer control gate structure can be formed using standard CMOS processes, significantly simplifying the manufacturing workflow while preserving the essential nonvolatile memory operation through quantum tunneling mechanisms.
Solution Approach 2:
The patent changes the operational parameters of the simplified single-layer gate structure by utilizing quantum tunneling effects and implementing specific voltage application sequences during program, erase, and read operations. These parameter changes enable the thin single-layer gate to achieve nonvolatile memory functionality that traditionally required thicker stacked gate structures.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The single-layer gate structure simplifies the fabrication process and enables efficient operation of nonvolatile memory devices by reducing complexity and aligning with CMOS processes used for logic devices, facilitating the creation of a system on chip (SoC).
Implementation Method 1
a tunneling line connected to the single-layer gate through a tunneling capacitor
Implementation Method 2
a well bias line connected to the single-layer gate through a coupling capacitor
Data Source
AI summary
A nonvolatile memory device includes a single-layer gate, a first area, and a second area. The first area includes a first well region, a first contact region arranged in the first well region, and source and drain regions arranged at both sides of the single-layer gate in the first well region. The second area includes a second well region, a second contact region arranged to overlap a part of the single-layer gate in the second well region, and a third contact region arranged in the second well region.