Single-Layer IC Package with Trimmed Conductive Layer
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Solution Overview
Problem
Current interconnecting substrates for semiconductor packaging, made of glass epoxy print substrates, face issues with heat treatment-induced defects and stress at the interface between external electrodes and insulating layers, leading to unreliable connections and potential distortion, which affects long-term reliability.
Innovation Solution
A method for fabricating an integrated circuit package with a single-layer ultra-thin interconnect structure, involving a base with a patterned conductive layer, where the surface is trimmed using chemical or mechanical processes to form electrical circuits and interconnections enclosed by masking materials, allowing for selective removal of the base to create internal and positioning openings, and subsequent wire bonding or flip-chip interconnection methods.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If glass epoxy print substrate is used as base core substrate for build-up multi-layered substrate, then interconnecting substrate can be fabricated with multiple layers and via holes, but heat treatments during fabrication and chip loading cause poor substrate condition, defects, faulty connections, distortion, and reduced long-term reliability
Solution Approach 1:
The patent extracts and removes the problematic glass epoxy print substrate from the package structure, retaining only the necessary conductive layers and interconnections. This eliminates the source of heat treatment-induced defects while preserving the multi-layer interconnect functionality through alternative substrate materials that are more heat-resistant.
Solution Approach 2:
The patent changes the material parameters of the substrate by replacing glass epoxy with alternative materials that have different thermal properties. This parameter change allows the substrate to withstand heat treatments without degrading, thereby improving connection reliability while maintaining the complex multi-layer structure.
2Ease of manufacture
If build-up multi-layered substrate is fabricated with heat treatments, then interconnection layers and via conductors can be formed, but the heat treatments cause defects and distortion that affect long-term reliability
Solution Approach 1:
The patent modifies the thermal parameters of the substrate material to withstand fabrication heat treatments without causing defects. By selecting materials with higher heat resistance, the fabrication process can proceed as before while avoiding the reliability issues caused by heat-induced distortion and defects.
Solution Approach 2:
The patent employs composite material structures that combine heat-resistant substrates with conductive layers, creating a multi-material system that can endure fabrication heat treatments. This composite approach maintains ease of manufacture while improving long-term reliability by eliminating heat-sensitive glass epoxy components.
3Ease of operation
If stress is structurally centered on the interface between external electrode terminal and insulating layer, then mounting can be performed, but opening defects occur at the interface, reducing mounting reliability
Solution Approach 1:
The patent removes the insulating layer from the mounting interface, eliminating the weak interface between external electrode terminals and insulating material. By exposing the conductive layer directly at the interface, the mounting structure gains improved mechanical strength and electrical connectivity, preventing opening defects while maintaining mounting capability.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enhances the reliability and mounting stability of the integrated circuit package by reducing defects and stress, ensuring a higher density of interconnections and improved long-term performance.
Implementation Method 1
the surface of the first patterned conductive layer is trimmed by using chemical process or mechanical grinding process or laser trimming process or plasma treatment
Implementation Method 2
the surface of the first patterned conductive layer is trimmed by using chemical process or mechanical grinding process or laser trimming process or plasma treatment
Implementation Method 3
the surface of the first patterned conductive layer is trimmed by using chemical process or mechanical grinding process or laser trimming process or plasma treatment
Implementation Method 4
the surface of the first patterned conductive layer is trimmed by using chemical process or mechanical grinding process or laser trimming process or plasma treatment
Implementation Method 5
subsequent wire bonding or flip-chip interconnection methods
Implementation Method 6
subsequent wire bonding or flip-chip interconnection methods
Data Source
AI summary
An integrated circuit packaging is described, including a plurality of electrical circuits developed using a first patterned conductive layer on a base, wherein an electrical circuit is formed by using a masking material, and an interconnection is developed between the electrical circuits, where the interconnection is disposed on at least one side of the first patterned conductive layer and masking material, in which the interconnection is enclosed with a second masking material to form the integrated circuit packaging.