Floating-Point Accumulator With Single-Layer Significand Shifters
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Solution Overview
Problem
Existing arithmetic logic circuits, particularly floating point multiply-and-accumulate units in high performance processors, face issues with exceptions that cause algorithms to stall or fail, leading to system failures in complex data processing settings like machine learning and inference engines.
Innovation Solution
A three-mode Floating point Carry-Save MAC (FP-CS-MAC) unit is implemented as a pipeline with six stages, including a BF16 Multiplier, Carry-Save Accumulate stage, and normalization and rounding, to handle exceptions without interrupting data flow operations, supporting BF16 and FP32 formats and handling denormalized numbers by truncation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If traditional floating point multiply-and-accumulate circuits are used, then arithmetic operations can be performed, but exceptions cause algorithms to stall or fail
Solution Approach 1:
The patent extracts the exception handling functionality from the main data flow path by implementing a separate exception detection and processing mechanism. The exception processing unit operates independently to detect and handle exceptions without interrupting the main multiply-and-accumulate data flow, thus maintaining productivity while improving reliability.
Solution Approach 2:
The patent introduces an intermediary exception processing unit that acts as a mediator between the arithmetic logic units and the control system. This unit intercepts exceptions, processes them appropriately, and returns control signals without allowing the exceptions to stall the main data flow, thereby resolving the contradiction between reliable exception handling and continuous productivity.
2Measurement precision
If floating point operations are performed with full precision and normalization, then accuracy is maintained, but processing speed is reduced
Solution Approach 1:
The patent applies partial normalization and rounding actions based on the specific operation mode. In accumulate mode, full normalization is performed to maintain precision. In multiply mode, partial normalization with rounding is sufficient, eliminating the need for complete normalization and thus improving speed while maintaining adequate precision for the operation type.
Solution Approach 2:
The patent implements dynamic adjustment of normalization and rounding operations based on the operation mode (multiply vs. accumulate). The normalization process is adapted dynamically: full normalization when accuracy is critical, and partial normalization with rounding when speed is prioritized, thus resolving the speed-precision tradeoff.
3Measurement precision
If denormalized numbers are fully processed, then precision is preserved, but processing time increases and system failures occur
Solution Approach 1:
The patent changes the processing parameter for denormalized numbers by detecting them and applying truncation instead of full normalization processing. This parameter change from complete processing to truncated processing reduces processing time significantly while preventing system failures associated with prolonged processing of denormalized values.
Solution Approach 2:
The patent performs preliminary detection of denormalized numbers before full processing occurs. By identifying denormalized values early in the pipeline, the system can apply truncation immediately rather than attempting full normalization, thus preserving sufficient precision while avoiding the time loss and system failures associated with complete denormalized number processing.
Data Source
AI summary
A floating-point accumulator circuit includes a floating-point input having an input significand field and a first shifter coupled to the input significand field and providing an output of the input significand field shifted by a first amount. A carry-save adder has a first, second, and third input and an output. The first input is coupled to the output of the first shifter and the output provides carry bits and sum bits representing a summation of the first input, the second input, and the third input as a significand of the accumulated value. Shifters are also coupled to the carry bits and the sum bits of the output of the carry-save adder to respectively provide the carry bits and the sum bits, both shifted by a second amount, to the second input and the third input of the carry-save adder.