Single-Layer Semiconductor Substrate With 3D-Printed Interconnects
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Solution Overview
Problem
The semiconductor packaging industry faces high costs due to complex interconnection processes, and existing facilities struggle to produce customized semiconductor chips for diverse applications such as IT, AI, vehicles, and smart factories.
Innovation Solution
The implementation of 3D printing technology for customized semiconductor packaging allows for the simplification of interconnection processes, reduction of costs, and creation of customized substrate shapes and interconnection structures, thereby optimizing process costs.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional interconnection processes are used for semiconductor packaging, then electrical connection between semiconductor parts is achieved, but costs of interconnection processes occupy most of the costs of semiconductor packaging and increase sharply as structure becomes complicated
Solution Approach 1:
The patent combines the substrate formation process and interconnection structure formation process into a single 3D printing step. The support structure is printed with embedded conductive materials (silver paste, copper, or aluminum) directly forming the interconnection pathways, eliminating separate interconnection processes and reducing manufacturing costs while maintaining electrical connection reliability
Solution Approach 2:
The support structure serves multiple functions simultaneously: it provides mechanical support during printing, forms the final substrate body, and creates the interconnection structures through embedded conductive materials. This multi-functionality reduces the number of separate manufacturing steps and associated costs
2Productivity
If conventional semiconductor production facilities are used, then standardized semiconductor chips are produced, but it is difficult to solve customized semiconductor chip demands for diverse applications
Solution Approach 1:
The 3D printing process enables dynamic customization of substrate shapes and interconnection structures based on specific application requirements. The support structure can be digitally designed and printed with varying geometries, conductive material distributions, and interconnection patterns, allowing rapid adaptation to different semiconductor chip customization needs without retooling
Solution Approach 2:
The patent enables parameter changes in substrate geometry, interconnection patterns, and conductive material placement through digital design modifications. This allows the same 3D printing facility to produce diverse customized semiconductor packages by changing digital parameters rather than physical tooling
3Reliability
If complex interconnection structures are created to improve chip performance, then electrical connection distance and number between semiconductor parts increase, but costs are increased sharply
Solution Approach 1:
The patent transitions from planar interconnection structures to three-dimensional interconnection pathways by embedding conductive materials within the volumetric support structure. This enables complex electrical connections to be formed through the third dimension, reducing the number of interconnection layers needed and simplifying the manufacturing process while maintaining or improving chip performance
Data Source
AI summary
According to various embodiments, a substrate for electrical connection between electronic components may include: a body having a single layer structure; and at least one interconnect having a conductivity formed inside the body, wherein the at least one interconnect includes one side and the other side exposed to the outside of the body, and a line connecting the one side and the other side, and wherein the line is crossed in a transverse direction or a longitudinal direction through the inside of the body of the single layer structure, and may be implemented to have a specific curvature in some sections. Other various embodiments are possible.