Single-Layered Floating Gate Nonvolatile Memory Devices
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Solution Overview
Problem
Existing nonvolatile memory devices with stacked gate structures are complex and require control gate electrodes, whereas single-layered floating gate devices without control gates are less efficient in terms of memory cell scaling and performance.
Innovation Solution
A nonvolatile memory device design featuring single-layered floating gates that overlap with sidewall surfaces of a drain mesa, allowing for increased coupling capacitance without expanding the cell's planar area, enabling efficient programming and erasure operations, and allowing twin cells to share a drain mesa for enhanced bit density.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a stacked gate structure with control gate electrode is used, then memory cell performance and reliability are improved, but device complexity and manufacturing process difficulty increase
Solution Approach 1:
The invention extracts and removes the control gate electrode from the stacked gate structure, retaining only the floating gate. This simplifies the device structure while maintaining the essential charge storage function, thereby reducing manufacturing complexity without completely sacrificing memory cell performance
Solution Approach 2:
The invention changes the structural parameters by transitioning from a multi-layer stacked gate to a single-layer floating gate configuration. This parameter change simplifies the device architecture and reduces the number of fabrication steps required
2Device complexity
If a single-layered floating gate without control gate is used, then device complexity is reduced and manufacturing is simplified, but coupling capacitance and programming efficiency deteriorate
Solution Approach 1:
The invention transitions from a planar gate structure to a three-dimensional configuration where the floating gate extends along the sidewall surface of the drain mesa. This vertical/dimensional extension increases the effective coupling area and capacitance without adding horizontal planar complexity
Solution Approach 2:
The floating gate is nested along the sidewall surface of the drain mesa, utilizing the vertical space and surface area of the existing drain structure. This nesting approach maximizes the coupling interface between the gate and channel region without requiring additional lateral space or complex multi-layer stacking
3Use of energy by moving object
If floating gate extends along sidewall surface of drain mesa, then coupling capacitance increases and programming efficiency improves, but manufacturing precision requirements increase
Solution Approach 1:
The invention merges the formation of the floating gate with the existing drain mesa structure. By utilizing the sidewall surface of the already-formed drain mesa as the template, the floating gate self-aligns to the correct position, reducing the need for separate high-precision alignment steps
4Area of stationary object
If twin cells share a drain mesa, then bit density and area efficiency are improved, but isolation and cross-talk control become more difficult
Solution Approach 1:
The invention segments the substrate into distinct regions using isolation layers that physically divide adjacent twin cells. This segmentation approach allows shared drain mesas to be electrically isolated from each other, preventing cross-talk while maintaining the area efficiency benefits of the shared structure
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The design enhances memory cell performance by increasing coupling ratios, allowing for scalable memory devices with improved programming and erasure efficiency, and enables the storage of multiple bits in reduced cell area, facilitating integration into system-on-chip technologies.
Implementation Method 1
overlapping with a sidewall surface of the drain mesa... increasing coupling capacitance
Data Source
AI summary
A nonvolatile memory device includes a plurality of twin cells arrayed on a substrate. Each of the plurality of twin cells includes a drain mesa protruding from a surface of a substrate. A first source and a second source are disposed in the substrate and spaced apart from the drain mesa. A first floating gate overlaps with a first sidewall surface of the drain mesa and extends onto the first source, and a second floating gate overlaps with a second sidewall surface of the drain mesa and extends onto the second source. Related methods are also provided.