Single-Layered Gate Nonvolatile Memory for SoC Integration
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Solution Overview
Problem
The integration of EEPROMs with logic devices in a system-on-chip (SoC) is complicated due to the difference in gate structures, with EEPROMs using a stacked gate structure and logic devices using a single gate structure, making fabrication procedures complex.
Innovation Solution
A nonvolatile memory device with a single-layered gate structure is developed, featuring a floating gate, a selection gate, and a dielectric layer, forming both horizontal and vertical capacitors to enhance coupling efficiency and simplify the fabrication process by aligning with CMOS processes used for logic devices.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a stacked gate structure is used for EEPROM memory cells, then data storage capability is improved, but fabrication complexity increases when integrating with logic devices
Solution Approach 1:
The patent transitions from a conventional vertical stacked gate structure to a horizontal single-layered gate structure. The gate electrode is positioned laterally adjacent to the active region rather than vertically above it, changing the spatial dimension of the gate configuration. This dimensional change enables compatibility with standard CMOS fabrication processes while maintaining EEPROM functionality through lateral coupling between the gate electrode and active region.
Solution Approach 2:
The single-layered horizontal gate structure serves multiple functions: it acts as the control gate for the EEPROM memory cell while being compatible with the single-gate transistor structure used in logic devices. This universal structure allows both memory and logic components to be fabricated using the same CMOS process steps, eliminating the need for separate stacked gate fabrication procedures and enabling true system-on-chip integration.
2Ease of manufacture
If a single-layered gate structure is used, then fabrication compatibility with logic devices is improved, but coupling efficiency may be reduced
Solution Approach 1:
The patent optimizes the local geometric parameters of the horizontal gate structure to enhance coupling efficiency. The gate electrode is positioned at a specific lateral distance from the active region, and its width and length are carefully designed to maximize the electric field coupling between the gate and the channel. The dielectric layer thickness between the gate electrode and active region is also optimized to achieve strong coupling while maintaining fabrication compatibility with CMOS processes.
Solution Approach 2:
The patent employs parameter optimization to achieve both fabrication compatibility and high coupling efficiency. By adjusting critical dimensions such as gate electrode width, gate-to-active-region spacing, and dielectric layer thickness, the design achieves strong electrical coupling for reliable memory operation while maintaining compatibility with standard CMOS fabrication tolerances and process capabilities.
3Reliability
If conventional stacked gate EEPROM structure is used, then memory functionality is achieved, but active region loss increases during fabrication
Solution Approach 1:
By changing from a vertical stacked gate configuration to a horizontal single-layered gate configuration, the patent eliminates the need for complex alignment steps that cause active region loss. The lateral positioning of the gate electrode allows for more tolerant alignment processes, reducing material waste and improving yield during fabrication.
Solution Approach 2:
The horizontal gate structure is formed using preliminary CMOS-compatible fabrication steps that define the gate electrode position before active region formation. This preliminary structuring allows subsequent processing steps to be performed with greater precision, minimizing active region loss and improving overall fabrication efficiency.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The single-layered gate structure increases coupling efficiency and simplifies the fabrication process, allowing for easier integration of EEPROMs with logic devices in a system-on-chip, improving the planarization process and reducing active region loss.
Implementation Method 1
a dielectric layer disposed between the floating gate and the selection gate, wherein a stack of the dielectric layer, the floating gate and the selection gate forms a first capacitor in a horizontal structure
Implementation Method 2
a well region disposed in the second active region and coupled to the floating gate, wherein a stack of the well region and the floating gate forms a second capacitor in a vertical structure
Data Source
AI summary
A nonvolatile memory device includes a first active region and a second active region separated from each other; a floating gate crossing the first active region, and disposed such that an end thereof overlaps with the second active region; a selection gate crossing the first active region, and disposed side by side with and coupled to the floating gate; a dielectric layer disposed between the floating gate and the selection gate, wherein a stack of the dielectric layer, the floating gate and the selection gate forms a first capacitor in a horizontal structure; a well region disposed in the second active region and coupled to the floating gate, wherein a stack of the well region and the floating gate forms a second capacitor in a vertical structure; and a contact commonly coupled to the well region and the selection gate.