Single LC VCO Clock Generation with Fractional-N Range Extension
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Solution Overview
Problem
Current wide frequency range clock generation systems require multiple inductor-capacitor voltage controlled oscillators (LC VCOs), leading to large silicon area usage and increased power consumption due to the need for multiple large inductor coils, while failing to produce low-jitter clock signals with sufficient tuning range.
Innovation Solution
A system utilizing a single inductor-capacitor voltage controlled oscillator (LC VCO) combined with an array of fractional-N dividers, which allows for a continuous frequency range by properly choosing the number and fractional divide ratios of the dividers, reducing silicon area and achieving low jitter and superior signal quality.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If multiple parallel voltage controlled oscillators (VCOs) are used to cover wide frequency range, then frequency coverage is improved, but silicon area consumption increases
Solution Approach 1:
The frequency range is segmented into multiple bands, with each band covered by a separate VCO. A frequency selection circuit then selects the appropriate VCO output based on the desired frequency range, enabling wide frequency coverage while using fewer oscillators than a single-wideband design would require.
Solution Approach 2:
Each VCO is designed to cover a specific frequency band universally, and through the frequency selection circuit, any of these VCOs can be activated to meet different frequency requirements. This multi-functional approach allows a single oscillator bank to replace what would otherwise require multiple dedicated oscillators for different frequency ranges.
2Adaptability or versatility
If multiple inductor-capacitor voltage controlled oscillators (LC VCOs) are used, then frequency tuning range is improved, but power consumption increases
Solution Approach 1:
The frequency tuning range is divided into multiple segments, with each LC VCO responsible for a specific segment. The frequency selection circuit activates only the VCO needed for the current operating frequency, thereby reducing power consumption compared to running multiple VCOs simultaneously or using a single wideband VCO that would consume more power across its entire range.
Solution Approach 2:
When a particular frequency band is not needed, the corresponding LC VCO is turned off to save power. The system recovers by activating a different VCO when the frequency requirement changes, ensuring that only the necessary oscillator consumes power at any given time.
3Reliability
If multiple large inductor coils are used, then frequency stability is improved, but device complexity increases
Solution Approach 1:
Instead of using one large inductor coil designed to cover the entire frequency range, the system segments the frequency range and uses multiple smaller inductor coils, each optimized for a specific band. This segmentation maintains frequency stability within each band while reducing the complexity of designing and implementing a single large inductor that would need to operate effectively across the entire frequency spectrum.
Solution Approach 2:
The inductor parameters (inductance value) are changed across different VCOs to match their respective frequency bands. Each VCO uses an inductor with parameters optimized for its specific frequency range, improving frequency stability without requiring a single complex inductor design. The frequency selection circuit manages these parameter changes by selecting the appropriate VCO.
Data Source
AI summary
A system for wide frequency range clock generation, includes: a phase lock loop (PLL) to generate a signal having a frequency; at least one fractional-N divider to divide the frequency of the signal; and a multiplexer to receive the signal from the PLL and an output signal from the at least one fractional-N divider, and to select the signal from the PLL or the output signal from the at least one fractional-N divider as a selected signal.


