Single LFSR Noise Generator for First-Order Response
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Solution Overview
Problem
Existing first-order noise generators using multiple linear feedback shift registers (LFSRs) face challenges in minimizing power consumption, device size, complexity, and cost while achieving a desired frequency response of 10 dB/decade, as they require multiple LFSRs and a high pass filter.
Innovation Solution
A first-order noise generator is implemented using a single shift register with N bit positions, where selected bit positions are tapped and a function is applied to generate a twos complement noise signal, eliminating the need for multiple LFSRs and a high pass filter, and achieving a first-order noise response.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If multiple LFSRs and a high pass filter are used to generate first-order noise signal, then the desired frequency response of 10 dB/decade is achieved, but power consumption, device size, and complexity increase
Solution Approach 1:
The patent merges the functions of multiple LFSRs and a high pass filter into a single LFSR implementation. By configuring one LFSR with specific tap positions and feedback logic, the circuit simultaneously generates the pseudorandom sequence and applies the first-order high-pass filtering effect, eliminating the need for separate components and reducing overall system complexity
Solution Approach 2:
The single LFSR is designed to perform multiple functions: it generates the pseudorandom noise sequence while simultaneously implementing the first-order high-pass filter response through its feedback configuration. This multi-functional approach allows one component to replace what previously required multiple dedicated components, reducing device complexity while maintaining the desired 10 dB/decade frequency response
2Manufacturing precision
If multiple LFSRs and a high pass filter are used to generate first-order noise signal, then the desired frequency response of 10 dB/decade is achieved, but power consumption increases
Solution Approach 1:
The patent merges the functions of multiple LFSRs and a high pass filter into a single LFSR implementation. By configuring one LFSR with specific tap positions and feedback logic, the circuit simultaneously generates the pseudorandom sequence and applies the first-order high-pass filtering effect, eliminating the need for separate components and reducing overall system complexity
Solution Approach 2:
The single LFSR is designed to perform multiple functions: it generates the pseudorandom noise sequence while simultaneously implementing the first-order high-pass filter response through its feedback configuration. This multi-functional approach allows one component to replace what previously required multiple dedicated components, reducing device complexity while maintaining the desired 10 dB/decade frequency response
3Manufacturing precision
If multiple LFSRs and a high pass filter are used to generate first-order noise signal, then the desired frequency response of 10 dB/decade is achieved, but device size increases
Solution Approach 1:
The patent merges the functions of multiple LFSRs and a high pass filter into a single LFSR implementation. By configuring one LFSR with specific tap positions and feedback logic, the circuit simultaneously generates the pseudorandom sequence and applies the first-order high-pass filtering effect, eliminating the need for separate components and reducing overall system complexity
Solution Approach 2:
The single LFSR is designed to perform multiple functions: it generates the pseudorandom noise sequence while simultaneously implementing the first-order high-pass filter response through its feedback configuration. This multi-functional approach allows one component to replace what previously required multiple dedicated components, reducing device complexity while maintaining the desired 10 dB/decade frequency response
Data Source
AI summary
A first-order signal generator (135). The generator comprises a shift register (210′) having a number N of bit positions. Each bit position is operable to store a binary value, the shift register operable to shift the binary value at each of the bit positions. The generator also comprises circuitry for tapping selected ones of the bit positions and circuitry for applying a function (220′) to each binary value in the selected ones of the bit positions to provide a function output. The generator also comprises circuitry for coupling the function output as an input to one of the bit positions. Lastly, the generator also comprises circuitry (230′) for outputting a first-order noise signal by coupling, as a twos complement number, each binary value in a plurality of the bit positions.


