Transmitter Receiver Single Line Clock Data Signal Transmission
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Solution Overview
Problem
Conventional systems require multiple transmission lines for clock and data signals, leading to increased area occupation and power consumption, and large area and power usage by clock synchronization circuits.
Innovation Solution
A transmitter and receiver system that transmits clock and data signals through a single transmission line, using phase and amplitude controlled signals, and includes aligners, transmission circuits, clock extraction circuits, and data recovery circuits to align and recover signals efficiently.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If multiple transmission lines are used to transmit clock and data signals separately, then signal transmission reliability is improved, but area occupation and power consumption increase
Solution Approach 1:
The patent combines clock signal and data signal transmission into a single transmission line by encoding both signals into one composite signal. The transmitter encodes the clock and data signals together, and the receiver extracts both signals from the single transmitted signal, thereby reducing the number of transmission lines from multiple to one while maintaining transmission reliability.
Solution Approach 2:
The single transmission line is designed to serve multiple functions: it simultaneously transmits both clock signal and data signal, replacing the conventional approach where separate lines are dedicated to each signal type. This multi-functional approach reduces the total number of transmission lines required.
2Reliability
If multiple transmission lines are used to transmit clock and data signals separately, then signal transmission reliability is improved, but power consumption increases
Solution Approach 1:
The patent merges clock and data signal transmission into a single transmission line, which reduces the total power consumption. By transmitting both signals through one line instead of multiple separate lines, the system reduces the cumulative power required for signal transmission while maintaining the reliability of signal delivery.
3Measurement precision
If a clock synchronization circuit such as PLL is used in the receiver to recover clock and data signals, then signal recovery accuracy is improved, but area occupation and power consumption increase
Solution Approach 1:
The patent extracts the clock signal directly from the transmitted composite signal at the receiver without requiring a complex clock synchronization circuit like PLL. By taking out the clock information directly from the transmitted signal during the encoding process, the system eliminates the need for large-area synchronization circuits while maintaining adequate clock recovery accuracy.
4Measurement precision
If a clock synchronization circuit such as PLL is used in the receiver to recover clock and data signals, then signal recovery accuracy is improved, but power consumption increases
Solution Approach 1:
The receiver extracts the clock signal directly from the transmitted signal without using power-intensive PLL circuits. This extraction method significantly reduces the power consumption associated with clock synchronization while maintaining the ability to recover accurate timing information for data signal reconstruction.
Data Source
AI summary
A system includes a transmitter including: an aligner configured to align the phases of an input clock signal and data signal; and a transmission circuit configured to generate a transmission signal of which the phase and amplitude are controlled according to the aligned clock signal and the aligned data signal. The system may also include a receiver including: a clock extraction circuit configured to extract a temporary clock signal from the transmission signal; a data extraction circuit configured to extract a temporary data signal from the transmission signal; a clock delay selector configured to generate the clock signal by delaying the temporary clock signal according to a value of the temporary data signal; and a data recovery circuit configured to sample the temporary data signal according to the clock signal outputted from the clock delay selector and output a data signal.