Single-Line Serial Data Transmission Circuit with Synthetic Signal
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Solution Overview
Problem
Conventional single-line serial data transmission circuits require complex control methods, large capacitors for power supply, and may result in increased circuit area, making them less efficient for high-speed data transmission and power management.
Innovation Solution
A single-line serial transmission circuit with a master and slave configuration using a data clock adder, data receiver, data clock separator, and active generator, where a synthetic signal combines clock and data signals for transmission, and a delay circuit is used to extract clock and data signals, along with a switching power supply circuit for protection functions.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If conventional single-line serial interfaces are used to connect multiple devices, then device connectivity is improved, but control complexity and circuit area increase
Solution Approach 1:
The patent divides the communication system into a master device and slave device with clearly defined roles. The master device controls the communication timing and data flow, while the slave device responds to master commands. This segmentation simplifies control logic compared to multi-device arbitration schemes.
Solution Approach 2:
The patent extracts the clock signal generation and communication control functions to the master device only. The slave device receives clock and data signals without needing to generate or control them, reducing overall system complexity while maintaining connectivity.
2Use of energy by moving object
If conventional single-line serial interfaces with power supply capability are used, then power feeding is improved, but circuit area increases due to large capacitor requirements
Solution Approach 1:
The patent combines power supply and data transmission functions into a single line. The same signal line carries both data and power, eliminating the need for separate power supply circuits and large capacitors, thus reducing circuit area while maintaining power feeding capability.
Solution Approach 2:
The single signal line serves multiple functions: data transmission, clock signal transmission, and power supply. This multi-functionality reduces the number of components needed and minimizes circuit area compared to dedicated separate lines for each function.
3Reliability
If clock and data signals are transmitted separately, then signal integrity is improved, but circuit area and transmission complexity increase
Solution Approach 1:
The patent merges clock and data signals into a single transmitted signal. The master device transmits both clock and data on one line, and the slave device separates them using timing relationships, reducing circuit area while maintaining signal integrity through the unified transmission approach.
4Productivity
If asynchronous data transmission without synchronization signals is used, then transmission speed is improved, but data accuracy and synchronization deteriorate
Solution Approach 1:
The patent uses periodic clock signals transmitted from the master device to synchronize data transmission. The regular clock pulses provide timing references that ensure accurate data sampling at the slave device while maintaining high transmission speeds through structured periodic communication.
Solution Approach 2:
The patent implements acknowledgment signals where the slave device confirms receipt of data to the master device. This feedback mechanism ensures data accuracy by verifying successful transmission while maintaining efficient communication through automated error detection and retransmission protocols.
Data Source
AI summary
A single-line serial data transmission circuit having a master circuit 1 and a slave circuit 4, the master circuit 1 having a data clock adder 2 for writes and a data receiver 3 for reads. The slave circuit 4 has an active generator 5, a data clock separator 6 for writes, and a data transmitter 7 for reads. The master circuit 1 and the slave circuit 4 are connected by one length of a signal line 8. When the master circuit 1 writes data to the slave circuit 4, a signal synthesized from a clock signal and a data signal is transmitted to the slave circuit 4 via the signal line 8 by the master circuit 1, and the clock signal and the data signal are extracted from the transmitted signal in the slave circuit 4 through the data clock separator 6.