Single-Line Full-Duplex Bus Using Time-Division Multiplexing
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Solution Overview
Problem
Existing server board communication systems require multiple signal lines and complex hardware schemes to achieve full-duplex communication, leading to increased hardware costs, reduced reliability, and difficulty in implementing digital circuits due to the need for multi-level signal transmission.
Innovation Solution
A single-level single-line full-duplex bus communication method using different coding formats and internal transmitter clocks allows for real-time data transmission over a single line, reducing the number of signal lines and hardware complexity by employing a high-level idle data format with specific level jump edges and low pulses for data framing.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If multiple signal lines are added to increase interactivity between boards, then communication effectiveness is improved, but hardware cost and connector area are increased
Solution Approach 1:
The patent merges multiple signal lines into a single line by using time-division multiplexing. Different types of signals (data transmission, acknowledgment, error detection) are transmitted sequentially on the same physical line at different time slots, eliminating the need for separate dedicated lines for each function and thus reducing the total number of signal lines required.
Solution Approach 2:
The single signal line is designed to perform multiple functions: carrying data bits, transmitting acknowledgment signals, and conveying error detection information. By making the signal line universal and capable of handling various communication tasks through time-division multiplexing, the system achieves high interactivity without requiring multiple dedicated lines.
2Reliability
If more signal lines are used to ensure communication reliability, then communication effectiveness is improved, but connector reliability is reduced
Solution Approach 1:
The patent combines multiple communication functions into a single signal line, reducing the number of connection points from multiple lines to one. This consolidation maintains communication reliability by ensuring all critical signals (data, acknowledgment, error detection) are transmitted through the same reliable single-line connection rather than being distributed across multiple potential failure points.
3Device complexity
If serial-to-parallel conversion is used to reduce signal lines, then hardware cost is reduced, but real-time interaction is compromised due to half-duplex mode
Solution Approach 1:
The patent implements full-duplex communication capability on a single line by dynamically switching between transmission and reception modes. The system can simultaneously transmit data in one direction while receiving data in the other direction, or switch between directions as needed, enabling real-time bidirectional interaction without the limitations of half-duplex serial communication.
Solution Approach 2:
The system uses periodic time-division multiplexing to alternate between transmission and reception phases. By organizing communication into periodic time slots where each party can transmit and receive in sequence, the system achieves full-duplex functionality on a single line, maintaining real-time interaction capability while reducing hardware complexity.
4Productivity
If multi-level mode is used for single-line full-duplex communication, then real-time interaction is achieved, but hardware complexity increases
Solution Approach 1:
The patent segments the communication protocol into distinct time slots and signal patterns that can be easily implemented with standard digital logic. By dividing the full-duplex communication into sequential transmission phases with clear start and stop markers, the system achieves real-time interaction capability using simple single-level signaling rather than complex multi-level encoding, thus reducing hardware complexity.
Data Source
AI summary
A single-level single-line full-duplex bus communication method and system are disclosed. The method includes: transmitting, by a first signal transceiver, data according to a first internal transmitter clock F1, simultaneously monitoring a level change on a bus, and parsing received data; transmitting, by a second signal transceiver, data according to a second internal transmitter clock F2, simultaneously monitoring the level change on the bus, and parsing received data; and communicating between the first and second signal transceivers by means of a single line, wherein the first and second transmitter clocks satisfy a relationship: F1>F2*(length of data unit+2). The system achieves single-level single-line full-duplex communication by using different coding formats and different internal transmitter clocks, whereby the number of signal lines can be reduced, single-level communication can be achieved by using universal digital levels, i.e., 0, 1, and the hardware implementation difficulty can be reduced.