Single-Line Power Sensing ADC With High Resolution and Low Power
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Solution Overview
Problem
Prior art analog to digital converters (ADCs) are power consumptive, provide low resolution, and are not suitable for applications with limited power budgets or high performance requirements due to inadequate resolution and accuracy.
Innovation Solution
The development of a novel ADC design that operates on a single line to both drive and sense analog signals, utilizing a comparator and digital circuit to convert analog signals into high-resolution digital formats with low power consumption, suitable for a wide range of applications including industrial and medical uses.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If prior art ADC designs are used, then conversion functionality is provided, but power consumption is high and resolution is low
Solution Approach 1:
The ADC is divided into multiple parallel sub-ADCs (e.g., 8 sub-ADCs for 3-bit resolution), where each sub-ADC processes a portion of the conversion task. This segmentation allows the system to achieve high resolution through parallel operation while keeping individual sub-ADCs simple and low-power, as they only need to perform basic comparisons rather than complex multi-bit conversions simultaneously.
Solution Approach 2:
The ADC employs periodic switching of sub-ADCs in groups, where different sets of sub-ADCs are activated in alternating time periods. This periodic action allows the same hardware resources to serve multiple resolution requirements at different times, reducing overall power consumption while maintaining high effective resolution through temporal multiplexing of the conversion process.
2Measurement precision
If high resolution is achieved through traditional ADC architectures, then measurement precision improves, but device complexity and power consumption increase
Solution Approach 1:
The complex high-resolution conversion task is segmented into multiple simple sub-ADC units, each handling a small portion of the resolution (e.g., 3-bit sub-ADCs for an 8-bit total resolution). Each sub-ADC uses simple comparator logic rather than complex flash or successive approximation circuits, dramatically reducing individual unit complexity while achieving high overall resolution through parallel combination.
Solution Approach 2:
Multiple simple sub-ADC outputs are merged through logical OR operations to produce the final high-resolution digital output. This merging approach allows the system to combine the results of several simple converters into a high-resolution measurement without requiring any single converter to be complex, thus achieving high resolution with low individual circuit complexity.
3Measurement precision
If multiple connections are used for sensor circuits (power, ground, signal), then sensing accuracy is maintained, but device complexity and power consumption increase
Solution Approach 1:
The ADC circuit performs multiple functions through its operational modes: it can provide power to the sensor through its output stage, sense the analog signal from the sensor, and convert the signal to digital format—all through the same circuitry. This multi-functionality eliminates the need for separate power supply and sensing paths, reducing overall system power consumption while maintaining sensing accuracy through integrated operation.
Data Source
AI summary
A high resolution analog to digital converter (ADC) with improved bandwidth senses an analog signal (e.g., a load current) to generate a digital signal. The ADC operates based on a load voltage produced based on charging of an element (e.g., a capacitor) by a load current and a digital to analog converter (DAC) output current (e.g., from a N-bit DAC). The ADC generates a digital output signal representative of a difference between the load voltage and a reference voltage. This digital output signal is used directly, or after digital signal processing, to operate an N-bit DAC to generate a DAC output current that tracks the load current. In addition, quantization noise is subtracted from the digital output signal thereby extending the operational bandwidth of the ADC. In certain examples, the operational bandwidth of the ADC extends up to 100s of kHz (e.g., 200-300 kHz), or even higher.