Single-Loop CDR Circuit With Adaptive PLL Bandwidth
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Solution Overview
Problem
Existing clock and data recovery (CDR) solutions in communication systems require additional control loops, external reference clock sources, and often suffer from jitter, lack of robust frequency acquisition, and imprecise phase locking, increasing cost, complexity, and size.
Innovation Solution
A CDR circuit arrangement utilizing a single phase-locked loop circuit without an external clock source, which selects between two reference signals based on operation mode to generate a synchronized oscillator signal for extracting a recovered data signal, employing multiple bandwidths for locking and synchronization modes to improve accuracy and reduce complexity.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If multiple control loops are used for CDR, then frequency acquisition robustness is improved, but device complexity increases
Solution Approach 1:
The patent combines multiple control loops into a single control loop that integrates both acquisition and tracking functions. The phase-locked loop circuit is configured to operate in different modes (acquisition mode and tracking mode) within a single loop structure, eliminating the need for separate acquisition and tracking loops while maintaining robust frequency acquisition and precise phase locking capabilities.
2Measurement precision
If external reference clock sources are used, then phase locking precision is improved, but cost increases
Solution Approach 1:
The patent implements a self-service mechanism where the circuit derives reference signals from the input signal itself rather than requiring external reference clock sources. The control unit extracts timing information from the incoming data stream and uses it to generate the common reference signal, making the system self-sufficient and eliminating the need for additional external components.
3Device complexity
If a single control loop is used, then device complexity is reduced, but phase locking precision deteriorates
Solution Approach 1:
The patent applies dynamic operation to the single control loop by enabling it to switch between different operating modes (acquisition mode and tracking mode) with different bandwidth characteristics. During acquisition mode, the loop operates with wider bandwidth for fast frequency acquisition, and during tracking mode, it operates with narrower bandwidth for precise phase locking, thus achieving high precision without requiring multiple loops.
4Device complexity
If fixed bandwidth is used in phase-locked loop, then circuit simplicity is improved, but adaptation to different operating modes deteriorates
Solution Approach 1:
The patent implements dynamic bandwidth adjustment in the phase-locked loop circuit, allowing the bandwidth to change based on the operating mode. The circuit includes a first bandwidth configuration for acquisition mode and a second bandwidth configuration for tracking mode, enabling the system to adapt to different operational requirements while maintaining manageable circuit complexity through systematic bandwidth switching.
Data Source
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AI summary
A circuit arrangement for clock and data recovery comprises a control unit (CTRL), a phase-locked loop circuit (PLL) and a sampling unit (SMPL). The control unit (CTRL) is configured to derive a first reference signal (PLSN) and a second reference signal (PLSD) from an input signal (SDIN). Furthermore, the control unit (CTRL) is configured to derive a common reference signal (FREF0) from one of the first reference signal (PLSN) and the second reference signal (PLSD), selected depending on a mode of operation of the circuit arrangement. The phase-locked loop circuit (PLL) is configured to generate an oscillator signal (SOSC) based on the common reference signal (FREF0). The sampling unit (SMPL9 is configured to extract a recovered data signal (RXD) from the input signal (SDIN).