Single Low-k Gate Spacer for FinFET Process
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Solution Overview
Problem
Current CMOS process flows face challenges in achieving equal n-type and p-type spacer thickness using low-k dielectric materials like SiOCN, as they lack the wet etch resistant qualities of SiBCN, and require silicon nitride cap layers for etch selectivity, leading to increased parasitic capacitance and reduced switching speed.
Innovation Solution
The method involves forming a high-k fin liner of hafnium and oxygen containing dielectrics to protect p-type epitaxial semiconductor material from forming in n-type regions and using oxidation to block n-type epitaxial material in p-type regions, allowing for a single low-k gate sidewall spacer integration without silicon nitride cap layers, thereby reducing etch steps and spacer slimming, and enabling equal spacer thickness for both n-type and p-type FinFETs.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Object-affected harmful factors
If low-k dielectric materials like SiOCN are used for gate sidewall spacers, then parasitic capacitance is reduced, but wet etch resistance is insufficient requiring additional silicon nitride cap layers
Solution Approach 1:
A high-k dielectric fin liner material (hafnium and oxygen containing dielectric) is introduced as an intermediary layer between the low-k dielectric gate sidewall spacer and the fin structure. This fin liner provides the necessary wet etch resistance during epitaxial growth, eliminating the need for silicon nitride cap layers while preserving the low parasitic capacitance benefit of the low-k dielectric spacer.
2Reliability
If silicon nitride cap layers are added for etch selectivity, then wet etch resistance is improved, but aspect ratio challenges increase and process window decreases
Solution Approach 1:
The invention changes the material parameter of the fin liner from conventional materials to high-k dielectric materials containing hafnium and oxygen. This material substitution provides superior wet etch resistance and etch selectivity without the geometric constraints imposed by thick silicon nitride cap layers, thereby improving the process window for tight pitch FinFET fabrication.
3Manufacturing precision
If multiple etch steps are used for selective spacer formation, then manufacturing precision is improved, but spacer slimming increases
Solution Approach 1:
The high-k dielectric fin liner is formed preliminarily before the low-k dielectric gate sidewall spacer deposition. This preliminary action establishes a protective barrier that prevents epitaxial semiconductor material formation on the fin structure during subsequent processing, enabling single spacer formation without multiple etch steps and reducing spacer slimming while maintaining thickness uniformity.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach reduces parasitic capacitance, decreases aspect ratio challenges in etching fin structures, and increases the process window in tight pitch areas by eliminating the need for silicon nitride cap layers, resulting in improved transistor performance with reduced spacer slimming and equal spacer widths for both n-type and p-type FinFETs.
Implementation Method 1
a remaining portion of the high-k dielectric fin liner remains on a second of said first and second plurality of fin structures to obstruct said first epitaxial semiconductor material from being formed thereon
Implementation Method 2
The first epitaxial semiconductor material is oxidized
Data Source
AI summary
A method of forming a semiconductor device that includes forming a high-k dielectric fin liner on the first plurality of fin structures in a first device region and a second plurality of fin structures in a second device region, and forming a gate structure including a low-k dielectric gate sidewall spacer on the channel region of the first and second plurality of fin structures. A first epitaxial semiconductor material on the first plurality of fin structures from which the high-k dielectric fin liner has been removed. The first epitaxial semiconductor material is then oxidized, and a remaining portion of the high-k dielectric fin liner is removed. A second epitaxial semiconductor material is formed on the second plurality of fin structures.