Single-Mask SOI Piezoresistive Accelerometer Fabrication
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Solution Overview
Problem
The fabrication of piezoresistive accelerometers is complex and costly due to the need for multiple masks and additional doping steps, and they are limited by pn-junctions that cause high leakage currents at temperatures above 150° C, restricting their operational range.
Innovation Solution
A single-mask fabrication process using Silicon-on-Insulator (SOI) wafers with selected resistivity eliminates the need for pn-junctions and additional doping, allowing all components of the accelerometer to be defined simultaneously, including piezoresistors and conductors, which can operate at higher temperatures.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If multiple masks and additional doping steps are used to fabricate piezoresistive accelerometers, then the fabrication precision and component isolation are improved, but the device complexity and manufacturing cost increase
Solution Approach 1:
The patent combines multiple fabrication steps (doping, mask alignment, etching) into a single wet etching process that defines all components simultaneously. The SOI wafer structure integrates the substrate, device layer, and isolation layer into one monolithic structure, eliminating the need for separate doping steps and multiple masks that would otherwise be required to achieve proper component isolation.
Solution Approach 2:
The single wet etching process serves multiple functions simultaneously: it defines piezoresistors, conductors, suspension beams, and proof mass boundaries in one operation. The SOI wafer itself provides both the mechanical support structure and the electrical isolation, making the fabrication process universally applicable to all accelerometer components without requiring component-specific processing steps.
2Manufacturing precision
If pn-junctions are used to define piezoresistive components, then the component isolation is improved, but the reliability at high temperatures deteriorates due to high leakage currents
Solution Approach 1:
The patent extracts the pn-junction isolation mechanism from the fabrication process entirely. Instead of relying on doped pn-junctions to isolate piezoresistive components, the invention uses the inherent physical structure of the SOI wafer, where the undoped device layer is naturally isolated from the substrate by the silicon dioxide isolation layer, eliminating temperature-dependent leakage currents.
Solution Approach 2:
The patent changes the isolation mechanism from electrical (pn-junction depletion regions) to physical (silicon dioxide layer). This parameter change transforms the isolation property from being temperature-sensitive to being temperature-stable, as the silicon dioxide layer maintains its insulating properties across a wide temperature range without generating leakage currents.
3Manufacturing precision
If additional doping steps are performed to create highly-doped conductors and lightly-doped piezoresistors, then the electrical conductivity control is improved, but the manufacturing time and process complexity increase
Solution Approach 1:
The patent employs self-service through the SOI wafer structure, where the device layer's inherent properties provide both the piezoresistive effect and conductor pathways without requiring external doping interventions. The wet etching process selectively removes material based on the existing layer structure, allowing the device layer to self-define both high-resistance piezoresistors and low-resistance conductors through its geometric configuration rather than doping concentration.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach reduces fabrication complexity and cost, enabling piezoresistive accelerometers to function effectively at higher temperatures and simplifies the manufacturing process while maintaining sensitivity and accuracy for acceleration measurements.
Implementation Method 1
piezoresistive accelerometers
Data Source
AI summary
An accelerometer and a method of fabricating an integrated accelerometer comprises the steps of providing an SOI wafer with a selected resistivity to eliminate any need for additional doping of the SOI wafer, providing a single mask on the SOI wafer, and simultaneously defining all components of the accelerometer in the SOI wafer without using any pn-junctions to define any piezoresistive components and to provide the same resistivity of all components. The step of simultaneously defining all components of the accelerometer in the SOI wafer comprises defining all components of a linear or angular accelerometer.