Single Masking Step for Multi-Tier Memory Cell Arrays
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Solution Overview
Problem
Existing methods for forming arrays of memory cells require multiple masking steps and complex fabrication processes, which can be inefficient and prone to errors, especially when dealing with multiple tiers of memory cells.
Innovation Solution
A method is developed to form arrays of memory cells using a single masking step for patterning shared conductive lines across elevationally-outer and inner-tier memory cells, reducing the complexity of fabrication and potentially improving the efficiency and accuracy of the process.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If multiple masking steps are used for patterning conductive lines in multi-tier memory cell arrays, then manufacturing precision can be maintained for each tier, but device complexity and fabrication time increase significantly
Solution Approach 1:
The patent combines multiple masking steps into a single masking operation by designing a unified pattern that simultaneously defines conductive lines for both inner-tier and outer-tier memory cells. This merging approach reduces fabrication complexity while maintaining patterning precision through careful pattern design that accounts for both tiers in one masking step.
Solution Approach 2:
The patent segments the conductive line structures into distinct inner-tier and outer-tier components that can be selectively formed from a single masked pattern. By dividing the final structure into elevationally-separated tiers, the patent enables complex multi-tier architecture to be built from a simpler single-step masking process.
2Manufacturing precision
If multiple masking steps are used for forming multi-tier memory cell arrays, then each tier can be precisely patterned, but productivity decreases due to increased fabrication time
Solution Approach 1:
The patent merges the patterning operations for multiple tiers into a single masking step, directly improving productivity by reducing the number of sequential fabrication steps. The unified masking pattern enables simultaneous definition of all conductive lines across tiers, eliminating the time penalty of multiple separate masking operations while preserving patterning accuracy through geometric design.
3Manufacturing precision
If complex fabrication processes with multiple masking steps are used, then manufacturing precision can be maintained, but loss of time increases due to extended fabrication cycles
Solution Approach 1:
The patent combines multiple time-consuming masking steps into a single operation, directly reducing fabrication cycle time. The unified masking approach eliminates the sequential time penalty of multiple steps while maintaining precision through a carefully designed pattern that simultaneously defines all required conductive lines for inner-tier and outer-tier memory cells.
Data Source
AI summary
A method of forming an array of memory cells, where the array comprises an elevationally-inner tier of memory cells comprising spaced-inner-tier-lower-first-conductive lines and inner-tier-programmable material directly there-above, an elevationally-outer tier of memory cells comprising spaced-outer-tier-lower-first-conductive lines and outer-tier-programmable material directly there-above, and spaced-upper-second-conductive lines that are electrically shared by the outer-tier memory cells and the inner-tier memory cells, comprises depositing conductor material for all of the shared-spaced-upper-second-conductive lines. All of the conductor material for all of the shared-spaced-upper-second-conductive lines is patterned using only a single masking step. Other method embodiments and arrays of memory cells independent of method of manufacture are disclosed.