Single Metal Layer Interposer for Low-Profile IC Packaging

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Solution Overview

Problem

The existing methods for manufacturing interposer substrates in integrated circuit packaging are complex and costly, particularly due to the need for routability of inputs and outputs, which complicates the production of laminate interposers and substrates, hindering the development of smaller, more efficient semiconductor chip packages.

Innovation Solution

A method involving a base substrate with an integrated circuit die and vertical interconnects, where a single metal layer interposer is formed with a dielectric layer and routing pattern, allowing for coplanar interposer contacts and traces, and mounted on the vertical interconnects, simplifying the manufacturing process and reducing costs.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Adaptability or versatility

If a laminate interposer with multiple metal layers is used to achieve routability of inputs and outputs, then the routing capability is improved, but the manufacturing complexity and cost increase

Engineering Contradiction:
Improverouting capabilityVSAvoidmanufacturing complexity
Core Design Contradiction:
Adaptability or versatilityVSDevice complexity

Solution Approach 1:

The patent extracts the essential routing function from complex multi-layer laminate interposers and implements it using a single metal layer with strategic via holes and trace routing. This extraction maintains the necessary routing capability while eliminating the complexity of multiple metal layers, dielectric layers, and associated manufacturing processes.

Inventive Principle:
Principle #2Taking out (Extraction)

Solution Approach 2:

The patent employs a simpler, more cost-effective interposer structure that uses a single metal layer instead of expensive multi-layer laminates. This approach sacrifices some routing versatility but maintains sufficient functionality for the application, thereby reducing manufacturing complexity and cost.

Inventive Principle:
Principle #27Cheap short-living objects (Disposable)

2Adaptability or versatility

If a laminate interposer is used to provide routing patterns, then the routing functionality is improved, but the package height increases

Engineering Contradiction:
Improverouting functionalityVSAvoidpackage height
Core Design Contradiction:
Adaptability or versatilityVSLength of moving object

Solution Approach 1:

The patent extracts the routing functionality from thick multi-layer laminate structures and implements it in a single metal layer, thereby maintaining routing capability while significantly reducing the vertical space required and thus the overall package height.

Inventive Principle:
Principle #2Taking out (Extraction)

3Ease of manufacture

If a single metal layer interposer is used to reduce manufacturing complexity, then the ease of manufacture is improved, but the routing capability for high I/O signals may be insufficient

Engineering Contradiction:
Improvemanufacturing simplicityVSAvoidrouting capability
Core Design Contradiction:
Ease of manufactureVSAdaptability or versatility

Solution Approach 1:

The patent uses a single metal layer with strategically placed via holes and traces to provide partial routing capability that is sufficient for the application's needs. This partial action approach maintains ease of manufacture while providing adequate routing functionality without the excessive complexity of full multi-layer structures.

Inventive Principle:
Principle #16Partial or excessive action

Data Source

PatentUS9299650B1Integrated circuit packaging system with single metal layer interposer and method of manufacture thereof
Publication Date: 2016.03.29 STATS CHIPPAC MANAGEMENT PTE LTD
  • US9299650B1 patent drawing
  • US9299650B1 patent drawing
  • US9299650B1 patent drawing

AI summary

An integrated circuit packaging system and method of manufacture thereof including: a base substrate; an integrated circuit die on the base substrate; vertical interconnects attached to the base substrate around the integrated circuit die; and a single metal layer interposer mounted on the vertical interconnects, the single metal layer interposer including: a routing pattern having interposer contacts and traces, and a dielectric layer on the interposer contacts and traces, a top surface of the interposer contacts coplanar with a top surface of the dielectric layer.